產品詳細資料

Sample rate (max) (Msps) 1000, 2000 Resolution (Bits) 10 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 56.8 ENOB (bit) 9 SFDR (dB) 67.6 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 100 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 1000, 2000 Resolution (Bits) 10 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 56.8 ENOB (bit) 9 SFDR (dB) 67.6 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 100 Radiation, SEL (MeV·cm2/mg) 120
CCGA (NAA) 376 780.6436 mm² 27.94 x 27.94
  • Total Ionizing Dose 100 krad(Si)
  • Single Event Latch-Up 120 Mev-cm2/mg
  • Excellent Accuracy and Dynamic Performance
  • Low Power Consumption
  • R/W SPI Interface for Extended Control Mode
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Ability to Interleave the 2 Channels to Operate 1 Channel at Twice the Conversion Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-Bit Gain and 12-Bit Plus Sign Offset Adjustments
  • Option of 1:2 Demuxed or 1:1 Non-demuxed LVDS Outputs
  • Auto-sync Feature for Multi-chip Systems
  • Single 1.9 ±0.1-V Power Supply
  • 376 Ceramic Pin Grid Array Package (28.2 mm x 28.2 mm x 3.1 mm with 1.27 mm ball-pitch)
  • Total Ionizing Dose 100 krad(Si)
  • Single Event Latch-Up 120 Mev-cm2/mg
  • Excellent Accuracy and Dynamic Performance
  • Low Power Consumption
  • R/W SPI Interface for Extended Control Mode
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Ability to Interleave the 2 Channels to Operate 1 Channel at Twice the Conversion Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-Bit Gain and 12-Bit Plus Sign Offset Adjustments
  • Option of 1:2 Demuxed or 1:1 Non-demuxed LVDS Outputs
  • Auto-sync Feature for Multi-chip Systems
  • Single 1.9 ±0.1-V Power Supply
  • 376 Ceramic Pin Grid Array Package (28.2 mm x 28.2 mm x 3.1 mm with 1.27 mm ball-pitch)

The ADC10D1000 is the latest advance in TI's Ultra-High-Speed ADC family of products. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS in dual channel mode or 2.0 GSPS in single channel mode. The ADC10D1000 achieves excellent accuracy and dynamic performance while consuming a typical 2.9 W of power. This space grade, Radiation Tolerant part is rad hard to a single event latch up level of greater than 120MeV and a total dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CPGA package rated over the temperature range of -55°C to +125°C.

The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. New features include an auto-sync feature for multi-chip synchronization, independent programmable15-bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the option of two's complement format for the digital output data. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 8.9 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) Consuming a typical 2.9 W in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9-V supply, this device is ensured to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demultiplexed Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower, but two times wider to relax data-capture timing margin. The two channels (I and Q) can also be interleaved (DES Mode) and used as a single 2.0 GSPS ADC to sample on the Q input. The output formatting is offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8 V and 1.2 V.

The ADC10D1000 is the latest advance in TI's Ultra-High-Speed ADC family of products. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS in dual channel mode or 2.0 GSPS in single channel mode. The ADC10D1000 achieves excellent accuracy and dynamic performance while consuming a typical 2.9 W of power. This space grade, Radiation Tolerant part is rad hard to a single event latch up level of greater than 120MeV and a total dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CPGA package rated over the temperature range of -55°C to +125°C.

The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. New features include an auto-sync feature for multi-chip synchronization, independent programmable15-bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the option of two's complement format for the digital output data. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 8.9 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) Consuming a typical 2.9 W in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9-V supply, this device is ensured to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demultiplexed Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower, but two times wider to relax data-capture timing margin. The two channels (I and Q) can also be interleaved (DES Mode) and used as a single 2.0 GSPS ADC to sample on the Q input. The output formatting is offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8 V and 1.2 V.

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類型 標題 日期
* Data sheet ADC10D1000QML Low-Power, 10-Bit, Dual 1-GSPS or Single 2-GSPS Analog-to-Digital Converter datasheet (Rev. G) PDF | HTML 2016年 12月 7日
* Radiation & reliability report ADC Single Event Upset Test Method 2012年 5月 7日
* Radiation & reliability report ADC10D1000CCMLS SEE Report 2012年 5月 7日
* Radiation & reliability report ADC10D1000CCMLS TID Report 2012年 5月 7日
* Radiation & reliability report CMOS Low Dose Rate Paper 2012年 5月 7日
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012年 5月 4日
Application brief DLA Approved Optimizations for QML Products (Rev. A) PDF | HTML 2024年 6月 5日
Selection guide TI Space Products (Rev. J) 2024年 2月 12日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023年 8月 31日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022年 11月 17日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
Application brief Understanding Op Amp Noise in Audio Circuits PDF | HTML 2021年 6月 14日
E-book Radiation Handbook for Electronics (Rev. A) 2019年 5月 21日
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 2017年 2月 3日
Application note Signal Chain Noise Figure Analysis 2014年 10月 29日
Application note Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 2014年 8月 6日
Application note AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 2013年 5月 1日
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 2012年 12月 18日
Product overview ADC12Dxx00RF Direct RF-Sampling ADC Family 2012年 5月 16日

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ADC-LD-BB — ADC 低失真平衡不平衡轉換器基板

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

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ADC10D1000QML IBIS Model

SNAM012.ZIP (42 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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CCGA (NAA) 376 Ultra Librarian

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