CDC7005
- High Performance 1:5 PLL Clock Synchronizer
- Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
- Synchronizes Frequencies up to 800 MHz (VCXO_IN)
- Supports Five Differential LVPECL Outputs
- Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
- All Outputs Are Synchronized
- Integrated Low-Noise OPA for External Low-Pass Filter
- Efficient Jitter Screening From Low PLL Loop Bandwidth
- Low-Phase Noise Characteristic
- Programmable Delay for Phase Adjustments
- Predivider Loop BW Adjustment
- SPI Controllable Division Setting
- Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
- 3.3-V Power Supply
- Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
- Industrial Temperature Range –40°C to 85°C
The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.
The CDC7005 is characterized for operation from –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet (Rev. L) | 2009/6/4 | |||
| Application brief | Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B) | 2009/12/15 | ||||
| 應用說明 | Basics of the CDC7005 Hold Function | 2006/4/13 | ||||
| 使用指南 | CDC7005 (QFN Package) Evaluation Module Manual (Rev. B) | 2006/3/28 | ||||
| 應用說明 | Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A) | 2005/7/19 | ||||
| 應用說明 | Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies | 2004/12/17 | ||||
| 使用指南 | TSW2000 Receive Clock JItter Cleaning EVM | 2004/6/28 | ||||
| 應用說明 | Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev | 2004/6/25 | ||||
| Product overview | ADS5500 + CDC7005 Product Bulletin | 2004/6/23 | ||||
| Product overview | TSW2000: TLK1201A & CDC7005 | 2004/6/23 | ||||
| 應用說明 | General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A) | 2003/12/16 |
設計與開發
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SCAC037 — CDC7005 SPI Software with Labview 8.0 Runtime Engine
CDC-CDCM7005-CALC — CDC7005 和 CDCM7005 PLL 迴路頻寬計算機
This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| BGA (ZVA) | 64 | Ultra Librarian |
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。