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CDCM7005-SP
- High Performance LVPECL and LVCMOS PLL
Clock Synchronizer - Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support
With Manual or Automatic Selection - Accepts LVCMOS Input Frequencies Up to
200 MHz - VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks - VCXO_IN Frequencies Up to 2 GHz (LVPECL)
- Outputs can be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL
Outputs or Up to 10 LVCMOS Outputs) - Output Frequency is Selectable by x1, /2, /3, /4,
/6, /8, /16 on Each Output
Individually - Efficient Jitter Cleaning from Low PLL Loop
Bandwidth - Low Phase Noise PLL Core
- Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs) - Wide Charge Pump Current Range From
200 µA to 3 mA - Analog and Digital PLL Lock Indication
- Provides VBB Bias Voltage Output for Single-
Ended Input Signals (VCXO_IN) - Frequency Hold Over Mode Improves Fail-Safe
Operation - Power-Up Control Forces LVPECL Outputs to Tri-
State at VCC < 1.5 V - SPI Controllable Device Setting
- 3.3-V Power Supply
- High-Performance 52 Pin Ceramic Quad Flat
Pack (HFG) - Rad-Tolerant : 50 kRad (Si) TID
- QML-V Qualified, SMD 5962-07230
- Military Temperature Range: –55°C to 125°C Tcase
- Engineering Evaluation (/EM) Samples are
Available(1)
The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.
VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.
The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.
All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.
The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).
技術文件
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檢視所有 11 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner datasheet (Rev. G) | PDF | HTML | 2015年 12月 3日 |
| * | SMD | CDCM7005-SP SMD 5962-07230 | 2016年 7月 8日 | |
| * | Radiation & reliability report | CDCM7005MHFG-V Radiation Test Report | 2014年 11月 12日 | |
| Application brief | DLA Approved Optimizations for QML Products (Rev. B) | PDF | HTML | 2024年 10月 23日 | |
| Selection guide | TI Space Products (Rev. J) | 2024年 2月 12日 | ||
| More literature | TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) | 2023年 8月 31日 | ||
| Application note | Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) | PDF | HTML | 2022年 11月 17日 | |
| Application note | Single-Event Effects Confidence Interval Calculations (Rev. A) | PDF | HTML | 2022年 10月 19日 | |
| E-book | Radiation Handbook for Electronics (Rev. A) | 2019年 5月 21日 | ||
| EVM User's guide | CDCM7005EVM-CVAL Evaluation Module (EVM) User's Guide | 2018年 9月 11日 | ||
| Application note | Phase Noise/Phase Jitter Performance of CDCM7005 | 2005年 7月 26日 |
設計與開發
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開發板
CDCM7005EVM-CVAL — CDCM7005-SP 評估模組
The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes an on-board voltage controlled crystal oscillator (VC(X)O) frequency to an external reference clock. The device operates up to 2 GHz. The PLL loop bandwidth and damping factor can be adjusted to (...)
使用指南: PDF
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模擬工具
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|---|---|---|
| CFP (HFG) | 52 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
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