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CDCM7005-SP

現行

抗輻射保證 (RHA) 3.3-V 高性能時脈抖動清除器和同步器

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產品規格表

CDCM7005-SP

現行
產品規格表 立即訂購

產品詳細資料

Number of input channels 2 Number of outputs 5 Features Programmable Delay Output frequency (min) (MHz) 0 Output frequency (max) (MHz) 1500 Output type LVCMOS, LVPECL Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Supply voltage (min) (V) 3 Supply voltage (max) (V) 3.6 Operating temperature range (°C) -55 to 125
Number of input channels 2 Number of outputs 5 Features Programmable Delay Output frequency (min) (MHz) 0 Output frequency (max) (MHz) 1500 Output type LVCMOS, LVPECL Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Supply voltage (min) (V) 3 Supply voltage (max) (V) 3.6 Operating temperature range (°C) -55 to 125
CFP (HFG) 52 363.474225 mm² 19.065 x 19.065
  • High Performance LVPECL and LVCMOS PLL
    Clock Synchronizer
  • Two Reference Clock Inputs (Primary and
    Secondary Clock) for Redundancy Support
    With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies Up to
    200 MHz
  • VCXO_IN Clock is Synchronized to One of the
    Two Reference Clocks
  • VCXO_IN Frequencies Up to 2 GHz (LVPECL)
  • Outputs can be a Combination of LVPECL and
    LVCMOS (Up to Five Differential LVPECL
    Outputs or Up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by x1, /2, /3, /4,
    /6, /8, /16 on Each Output
    Individually
  • Efficient Jitter Cleaning from Low PLL Loop
    Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and
    SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 µA to 3 mA
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-
    Ended Input Signals (VCXO_IN)
  • Frequency Hold Over Mode Improves Fail-Safe
    Operation
  • Power-Up Control Forces LVPECL Outputs to Tri-
    State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • High-Performance 52 Pin Ceramic Quad Flat
    Pack (HFG)
  • Rad-Tolerant : 50 kRad (Si) TID
  • QML-V Qualified, SMD 5962-07230
  • Military Temperature Range: –55°C to 125°C Tcase
  • Engineering Evaluation (/EM) Samples are
    Available(1)
  • High Performance LVPECL and LVCMOS PLL
    Clock Synchronizer
  • Two Reference Clock Inputs (Primary and
    Secondary Clock) for Redundancy Support
    With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies Up to
    200 MHz
  • VCXO_IN Clock is Synchronized to One of the
    Two Reference Clocks
  • VCXO_IN Frequencies Up to 2 GHz (LVPECL)
  • Outputs can be a Combination of LVPECL and
    LVCMOS (Up to Five Differential LVPECL
    Outputs or Up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by x1, /2, /3, /4,
    /6, /8, /16 on Each Output
    Individually
  • Efficient Jitter Cleaning from Low PLL Loop
    Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and
    SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 µA to 3 mA
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-
    Ended Input Signals (VCXO_IN)
  • Frequency Hold Over Mode Improves Fail-Safe
    Operation
  • Power-Up Control Forces LVPECL Outputs to Tri-
    State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • High-Performance 52 Pin Ceramic Quad Flat
    Pack (HFG)
  • Rad-Tolerant : 50 kRad (Si) TID
  • QML-V Qualified, SMD 5962-07230
  • Military Temperature Range: –55°C to 125°C Tcase
  • Engineering Evaluation (/EM) Samples are
    Available(1)

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).
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類型 標題 日期
* Data sheet CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner datasheet (Rev. G) PDF | HTML 2015年 12月 3日
* Radiation & reliability report CDCM7005-SP Single-Event Effects Report 2025年 6月 4日
* SMD CDCM7005-SP SMD 5962-07230 2016年 7月 8日
* Radiation & reliability report CDCM7005MHFG-V Radiation Test Report 2014年 11月 12日
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025年 6月 17日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025年 6月 10日
Selection guide TI Space Products (Rev. K) 2025年 4月 4日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025年 2月 20日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
E-book Radiation Handbook for Electronics (Rev. A) 2019年 5月 21日
Application note Phase Noise/Phase Jitter Performance of CDCM7005 2005年 7月 26日

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CDCM7005EVM-CVAL — CDCM7005-SP 評估模組

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes an on-board voltage controlled crystal oscillator (VC(X)O) frequency to an external reference clock. The device operates up to 2 GHz. The PLL loop bandwidth and damping factor can be adjusted to (...)

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SGLC002 — CDCM7005-SP EVM GUI

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時鐘抖動清除器
  • CDCM7005-SP — 抗輻射保證 (RHA) 3.3-V 高性能時脈抖動清除器和同步器
硬體開發
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模擬型號

CDCM7005-SP IBIS MODEL A

SLLM295.ZIP (36 KB) - IBIS Model
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CDCM7005-SP IBIS MODEL B

SLLM296.ZIP (36 KB) - IBIS Model
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模擬型號

CDCM7005-SP IBIS MODEL C

SLLM297.ZIP (36 KB) - IBIS Model
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