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邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

SN54AHCT74

現行

具有清除和預設功能的二路正緣觸發 D 型正反器

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產品規格表

SN54AHCT74

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Technology family AHCT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 70 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 20 Features Balanced outputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family AHCT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 70 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 20 Features Balanced outputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm² (— mm × — mm) LCCC (FK) 20 79.0321 mm² (— mm × — mm) CFP (W) 14 58.023 mm² (— mm × — mm)
  • Operating range of 4.5 V to 5.5 V
  • Low power consumption, 10-µA maximum I CC
  • ±8-mA output drive at 5 V
  • Inputs are TTL-voltage compatible
  • Latch-up performance exceeds 250 mA per JESD 17
  • Operating range of 4.5 V to 5.5 V
  • Low power consumption, 10-µA maximum I CC
  • ±8-mA output drive at 5 V
  • Inputs are TTL-voltage compatible
  • Latch-up performance exceeds 250 mA per JESD 17

The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SNxAHCT74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. R) PDF | HTML 2023/10/17
* SMD SN54AHCT74 SMD 5962-96861 2016/6/21

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