UC1875-SP

現行

抗輻射 QMLV、20-V、2-A 雙輸出全橋相移式 2-MHz PWM 控制器

產品詳細資料

Vin (max) (V) 18 Operating temperature range (°C) -55 to 125 Control mode Current, Feedforward, Voltage Topology Phase-shifted full bridge Rating Space Duty cycle (max) (%) 100
Vin (max) (V) 18 Operating temperature range (°C) -55 to 125 Control mode Current, Feedforward, Voltage Topology Phase-shifted full bridge Rating Space Duty cycle (max) (%) 100
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 24 130.5324 mm² 14.36 x 9.09
  • QML-V Qualified, SMD 5962-94555
  • Rad-Tolerant: 50 kRad (Si) TID(1)
  • Zero to 100% Duty Cycle Control
  • Programmable Output Turn-On Delay
  • Compatible with Voltage or Current Mode
    Topologies
  • Practical Operation at Switching Frequencies to
    1 MHz
  • Four 2-A Totem Pole Outputs
  • 10-MHz Error Amplifier
  • Undervoltage Lockout (UVLO)
  • Low Startup Current – 150 µA
  • Outputs Active Low During UVLO
  • Soft-Start Control
  • Latched Overcurrent Comparator With Full Cycle
    Restart
  • Trimmed Reference
  • QML-V Qualified, SMD 5962-94555
  • Rad-Tolerant: 50 kRad (Si) TID(1)
  • Zero to 100% Duty Cycle Control
  • Programmable Output Turn-On Delay
  • Compatible with Voltage or Current Mode
    Topologies
  • Practical Operation at Switching Frequencies to
    1 MHz
  • Four 2-A Totem Pole Outputs
  • 10-MHz Error Amplifier
  • Undervoltage Lockout (UVLO)
  • Low Startup Current – 150 µA
  • Outputs Active Low During UVLO
  • Soft-Start Control
  • Latched Overcurrent Comparator With Full Cycle
    Restart
  • Trimmed Reference

The UC1875-SP implements control of a bridge power stage by phase-shifting the switching of one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be configured to provide control in either voltage or current mode operation, with a separate overcurrent shutdown for fast fault protection.

A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair (A-B, C-D).

With the oscillator capable of operation at frequencies in excess of 2 MHz, overall switching frequencies to 1 MHz are practical. In addition to the standard free running mode, with the CLOCKSYNC pin, the user may configure these devices to accept an external clock synchronization signal, or may lock together up to 5 units with the operational frequency determined by the fastest device.

Protective features include an undervoltage lockout which maintains all outputs in an active-low state until the supply reaches a 10.75-V threshold. 1.5 hysteresis is built in for reliable, boot-strapped chip supply. Overcurrent protection is provided, and will latch the outputs in the OFF state within 70 ns of a fault. The current-fault circuitry implements full-cycle restart operation.

Additional features include an error amplifier with bandwidth in excess of 7 MHz, a 5-V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry.

This device is available in hermetically sealed cerdip, surface mount, and ceramic leadless chip carrier packages for –55°C to 125°C operation.

The UC1875-SP implements control of a bridge power stage by phase-shifting the switching of one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be configured to provide control in either voltage or current mode operation, with a separate overcurrent shutdown for fast fault protection.

A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair (A-B, C-D).

With the oscillator capable of operation at frequencies in excess of 2 MHz, overall switching frequencies to 1 MHz are practical. In addition to the standard free running mode, with the CLOCKSYNC pin, the user may configure these devices to accept an external clock synchronization signal, or may lock together up to 5 units with the operational frequency determined by the fastest device.

Protective features include an undervoltage lockout which maintains all outputs in an active-low state until the supply reaches a 10.75-V threshold. 1.5 hysteresis is built in for reliable, boot-strapped chip supply. Overcurrent protection is provided, and will latch the outputs in the OFF state within 70 ns of a fault. The current-fault circuitry implements full-cycle restart operation.

Additional features include an error amplifier with bandwidth in excess of 7 MHz, a 5-V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry.

This device is available in hermetically sealed cerdip, surface mount, and ceramic leadless chip carrier packages for –55°C to 125°C operation.

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類型 標題 日期
* Data sheet UC1875-SP Rad-Tolerant Class-V, Phase Shift Resonant Controller datasheet (Rev. B) PDF | HTML 2015年 12月 31日
* Radiation & reliability report UC1875-SP Neutron Displacement Damage (NDD) Characterization Report 2021年 10月 29日
* SMD UC1875-SP SMD 5962-94555 2016年 7月 8日
* Radiation & reliability report UC1875‐SP TID Report 2015年 3月 31日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023年 8月 31日
Application note QML flow, its importance, and obtaining lot information (Rev. C) 2023年 8月 30日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022年 11月 17日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
Selection guide TI Space Products (Rev. I) 2022年 3月 3日
Application note DLA Standard Microcircuit Drawings (SMD) and JAN Part Numbers Primer 2020年 8月 21日
Application note Hermetic Package Reflow Profiles, Termination Finishes, and Lead Trim and Form PDF | HTML 2020年 5月 18日
E-book Radiation Handbook for Electronics (Rev. A) 2019年 5月 21日
Application note Phase Shifted Full Bridge, Zero Voltage Transition Design Considerations (Rev. A) 2011年 1月 22日
More literature Seminar 800 Topic 5 - Fixed-Frequency Resonant-Switched PWM 2001年 2月 15日
More literature Seminar 900 Topic 3 - Designing a Phase-Shifted ZVT Power Converter 2001年 2月 15日
More literature Seminar 900 Topic 4 - 500-W 40-W/in3 Phase-Shifted ZVT Power Converter 2001年 2月 15日

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CFP (W) 24 檢視選項

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