UCC27624V
- Typical 5A peak source and sink drive current for each channel
- Input and enable pins capable of handling –10V
- Output capable of handling –2V transients
- Absolute maximum VDD voltage: 30V
- Wide VDD operating range from 9.5V to 26V with UVLO
- Two independent gate drive channels
- Independent enable function for each output
- Hysteretic-logic thresholds for high noise immunity
- VDD independent input thresholds (TTL compatible)
- Fast propagation delays (17ns typical)
- Fast rise and fall times (6ns and 10ns typical)
- 1ns typical delay matching between the two channels
- Two channels can be paralleled for higher drive current
- SOIC8 and VSSOP8 PowerPAD™ package options
- Operating junction temperature range of –40°C to 150°C
The UCC27624V is a dual-channel, high-speed, low-side gate driver that effectively drives MOSFET, IGBT and SiC power switches. UCC27624V has a typical peak drive strength of 5A, which reduces rise and fall times of the power switches, lowers switching losses, and increases efficiency. The devices fast propagation delay (17ns typical) yields better power stage efficiency by improving the deadtime optimization, pulse width utilization, control loop response, and transient performance of the system.
UCC27624V can handle –10V at its inputs, which improves robustness in systems with moderate ground bouncing. The inputs are independent of supply voltage and can be connected to most controller outputs for maximum control flexibility. An independent enable signal allows the power stage to be controlled independently of main control logic. In the event of a system fault, the gate driver can quickly shut-off by pulling enable low. Many high-frequency switching power supplies exhibit noise at the gate of the power device, which can get injected into the output pin on the gate driver and can cause the driver to malfunction. The devices transient reverse current and reverse voltage capability allow it to tolerate noise on the gate of the power device or pulse-transformer and avoid driver malfunction.
The UCC27624V also features undervoltage lockout (UVLO) for improved system robustness. When there is not enough bias voltage to fully enhance the power device, the gate driver output is held low by the strong internal pull down MOSFET.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | UCC27624V 30V, 5A, Dual-Channel, 8V-UVLO, Low-Side Gate Driver with –10V Input Capability datasheet | PDF | HTML | 2025年 3月 25日 |
| Product overview | UCC27624: Enabling Higher Efficiency in a Smaller Package | PDF | HTML | 2025年 3月 27日 | |
| Application note | Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs | PDF | HTML | 2024年 1月 22日 | |
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 |
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HVSSOP (DGN) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
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