|Package | PIN:||SOIC (D) | 8|
|Temp:||Q (-40 to 125)|
- Qualified for automotive applications
- AEC-Q100 qualified with the following results:
- Device temperature grade 1: –40°C to +125°C ambientoperating temperature
- Device HBM ESD classification level3A
- Device CDM ESD classification level C6
- Isolated bidirectional, I2C compatible, communication
- Supports up to 1-MHz operation
- 3-V to 5.5-V supply range
- Open-drain outputs With 3.5-mA Side 1 and 35-mA Side 2 sink current capability
- ±50-kV/µs transient immunity (Typical)
- Safety-related certifications:
- 4242-VPK isolation per DIN VDE V0884-11:2017-01
- 2500-VRMS isolation for 1 minute per UL1577
- CSA approval per IEC 60950-1 and IEC 62368-1 end equipmentstandards
- CQCbasic insulation per GB4943.1-2011
All trademarks are the property of their respective owners.
Texas Instruments ISO1540QDRQ1
The ISO1540-Q1and ISO1541-Q1 devices are low-power, bidirectional isolators that are compatible withI2C interfaces. These devices have logic input and output buffers thatare separated by Texas Instruments Capacitive Isolation technology using a silicon dioxide(SiO2) barrier. When used with isolated power supplies, these devices blockhigh voltages, isolate grounds, and prevent noise currents from entering the local ground andinterfering with or damaging sensitive circuitry.
This isolation technology provides for function, performance, size, and power consumptionadvantages when compared to optocouplers. The ISO1540-Q1 and ISO1541-Q1 devices enable a completeisolated I2C interface to be implemented within a small formfactor.
The ISO1540-Q1 has twoisolated bidirectional channels for clock and data lines while the ISO1541-Q1 has a bidirectional dataand a unidirectional clock channel. The ISO1541-Q1 is useful in applications that have a single master while theISO1540-Q1 is suitable formulti-master applications. For applications where clock stretching by the slave is possible, theISO1540-Q1 device should beused.
Isolated bidirectional communication is accomplished within these devices by offsettingthe low-level output voltage on side 1 to a value greater than the high-level input voltage on side1, thus preventing an internal logic latch that otherwise would occur with standard digitalisolators.