High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars


Design files


The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and oscilloscope applications. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated digital down Converter, features a JESD204B interface, and it captures signals up to 4GHz. This design showcases the clocking solution using the LMK04828, to achieve the synchronization between multiple ADC12J4000 signal chains using synchronized SYSREF.

  • Synchronization of multi-channel high speed ADCs
  • RF sampling ADC clocking solution
  • 4GHz high frequency input signal capture capability
  • Low-phase noise clocking solution for RF sampling ACC
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.


Reference design overview and verified performance test data

TIDRP85.PDF (398 K)

Detailed schematic diagram for design layout and components

TIDRP86.PDF (69 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRP87.PDF (1640 K)

Detailed overview of design layout for component placement

TIDRP89.ZIP (10462 K)

Files used for 3D models or 2D drawings of IC components

TIDCD12.ZIP (713 K)

Design file that contains information on physical board layer of design PCB

TIDRP88.PDF (2736 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

Buck converters (integrated switch)

TPS543274.5V to 18V Input, 3-A Synchronous Step-Down Converter

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
Direction-controlled voltage translators

SN74AVC4T7744-bit dual-supply bus transceiver with configurable voltage-level shifting and 3-state outputs

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC12J400012-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS749013-A, low-VIN (0.8-V) adjustable ultra-low-dropout voltage regulator with power good and enable

Data sheet: PDF | HTML
Noninverting buffers & drivers

SN74LVC1G125Single 1.65-V to 5.5-V buffer with 3-state outputs

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide High-Speed Multichannel ADC Clock for Oscilloscopes Reference Design Dec. 15, 2016

Related design resources

Hardware development

ADC12J4000EVM ADC12J4000 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter Evaluation Module LMK04828BEVM LMK04828 evaluation module

Reference designs

TIDA-00432 Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems TIDA-01015 4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers TIDA-01016 Clocking Reference Design for RF Sampling ADCs in Signal Analyzers and Wireless Testers TIDA-01021 Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers TIDA-01022 Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems TIDA-01023 High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers TIDA-01024 High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

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