Clock and Timing

Clock Jitter Cleaners – Tools & software

Featured evaluation modules

  • LMK04610EVM - Ultra-low noise and low power JESD204B compliant clock jitter cleaner with dual PLLs
  • LMK04828BEVM - Ultra-low noise JESD204B compliant clock jitter cleaners with dual loop PLLs
  • LMK04906BEVAL - Low noise clock jitter cleaner/multiplier with 6 programmable outputs
  • LMK04816BEVAL - 3-input low noise clock jitter cleaner with dual loop PLLs
  • LMK04808BEVAL - Low noise clock jitter cleaner with dual loop PLLs and integrated VCO
TI Designs
  • TIDA-00431 - RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
  • TIDA-00432 - Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
  • TIDA-00359 - Clocking Solution Reference Design for GSPS ADCs
  • TIDA-00826 - 50-Ohm 2-GHz Oscilloscope Front-end Reference Design
  • TIDEP0034 - 66AK2L06 DSP+ARM Processor with JESD204B Attach to Wideband ADCs and DACs

WEBENCH® Clock Architect

TI's WEBENCH Clock Architect online design tool makes the designer's life easier by generating complete clock-tree solutions. Multiple solutions are generated, each optimized for performance, cost or board space.

WEBENCH® Designer

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Software for device register programming.

Clock Design Tool

Offline tool for device selection, configuration and simulation, including loop filter design. Recommend using the new Webench® online tool.

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