Clock & timing

Clock jitter cleaners – Tools & software

Featured evaluation modules


Ultra-low noise and low power JESD204B compliant dual loop jitter cleaner.


Ultra low jitter synthesizer and jitter cleaner.


Low noise clock jitter cleaner/multiplier with 6 programmable outputs. 


3-input low noise clock jitter cleaner with dual loop PLLs.


Low noise clock jitter cleaner with dual loop PLLs and integrated VCO.

Featured TI designs

RF sampling 4-GSPS ADC reference design with 8-GHz DC-coupled differential amplifier.

Synchronization of JESD204B giga-sample ADCs using Xilinx platform for phased array radar systems.

Clocking solution reference design for GSPS ADCs.

50-Ohm 2-GHz oscilloscope front-end reference design.

6AK2L06 DSP+ARM processor with JESD204B attach to wideband ADCs and DACs.

Featured tools and software

WEBENCH® Clock Architect

This online design tool makes the designer's life easier by generating complete clock-tree solutions. Multiple solutions are generated, each optimized for performance, cost or board space.


Software for device register programming.

Clock Design Tool

Offline tool for device selection, configuration and simulation, including loop filter design. Recommend using the new Webench® online tool.