SGLS307P July   2006  – February 2018 TLK2711-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     External Component Interconnection
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 TTL Input Electrical Characteristics
    6. 7.6 Transmitter/Receiver Electrical Characteristics
    7. 7.7 Reference Clock (TXCLK) Timing Requirements
    8. 7.8 TTL Output Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Transmit Interface
      2. 8.3.2  Transmit Data Bus
      3. 8.3.3  Data Transmission Latency
      4. 8.3.4  8-Bit/10-Bit Encoder
      5. 8.3.5  Pseudo-Random Bit Stream (PRBS) Generator
      6. 8.3.6  Parallel to Serial
      7. 8.3.7  High-Speed Data Output
      8. 8.3.8  Receive Interface
      9. 8.3.9  Receive Data Bus
      10. 8.3.10 Data Reception Latency
      11. 8.3.11 Serial to Parallel
      12. 8.3.12 Comma Detect and 8-Bit/10-Bit Decoding
      13. 8.3.13 LOS Detection
      14. 8.3.14 PRBS Verification
      15. 8.3.15 Reference Clock Input
      16. 8.3.16 Operating Frequency Range
      17. 8.3.17 Testability
      18. 8.3.18 Loopback Testing
      19. 8.3.19 BIST
      20. 8.3.20 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
      2. 8.4.2 High-Speed I/O Directly-Coupled Mode
      3. 8.4.3 High-Speed I/O AC-Coupled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over parallel solutions, as well as scalability for higher data rates in the future.

The TLK2711-SP performs parallel-to-serial and serial-to-parallel data conversion. The clock extraction functions as a physical layer (PHY) interface device. The serial transceiver interface operates at a maximum speed of 2.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (TXCLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8b/10b) encoding format. The resulting 20-bit word is then transmitted differentially at 20× the reference clock (TXCLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the recovered clock (RXCLK). It then decodes the 20-bit wide data using the 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data pins (RXD0–RXD15). The outcome is an effective data payload of 1.28 to 2 Gbps (16 bits data × the frequency).

The TLK2711-SP is available in a 68-pin ceramic nonconductive tie-bar package (HFG).

NOTE

The errata noted in the commercial TLK2711 device titled Errata to the TLK2711, 1.6-to-2.7 GBPS Transceiver Data Sheet– PLL False Lock Problem does not apply to the TLK2711-SP device. The TLK2711-SP is functionally equivalent to the TLK2711A commercial device.

The TLK2711-SP provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, providing the protocol device with a functional self-check of the physical interface.

The TLK2711-SP has a LOS detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.

The TLK2711-SP allows users to implement redundant ports by connecting receive data bus pins from two TLK2711-SP devices together. Asserting the LCKREFN to a low state causes the receive data bus pins (RXD0 - RXD15, RXCLK, RKLSB, and RKMSB) to go to a high-impedance state if device is enabled (ENABLE = H). This places the device in a transmit-only mode, because the receiver is not tracking the data. LCKREFN must be de-asserted to a high state during power-on reset (see Power-On Reset section). If the device is disabled (ENABLE = L), then RKMSB will output the status of the LOS detector (active low = LOS ). All other receive outputs will remain high-impedance.

The TLK2711-SP I/Os are 3-V compatible. The TLK2711-SP is characterized for operation from –55°C to 125°C Tcase.

The TLK2711-SP is designed to be hot-plug capable. An on-chip power-on reset circuit holds the RXCLK low, and goes to high impedance on the parallel-side output signal pins, as well as TXP and TXN during power up.