SGLS307P July   2006  – February 2018 TLK2711-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     External Component Interconnection
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 TTL Input Electrical Characteristics
    6. 7.6 Transmitter/Receiver Electrical Characteristics
    7. 7.7 Reference Clock (TXCLK) Timing Requirements
    8. 7.8 TTL Output Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Transmit Interface
      2. 8.3.2  Transmit Data Bus
      3. 8.3.3  Data Transmission Latency
      4. 8.3.4  8-Bit/10-Bit Encoder
      5. 8.3.5  Pseudo-Random Bit Stream (PRBS) Generator
      6. 8.3.6  Parallel to Serial
      7. 8.3.7  High-Speed Data Output
      8. 8.3.8  Receive Interface
      9. 8.3.9  Receive Data Bus
      10. 8.3.10 Data Reception Latency
      11. 8.3.11 Serial to Parallel
      12. 8.3.12 Comma Detect and 8-Bit/10-Bit Decoding
      13. 8.3.13 LOS Detection
      14. 8.3.14 PRBS Verification
      15. 8.3.15 Reference Clock Input
      16. 8.3.16 Operating Frequency Range
      17. 8.3.17 Testability
      18. 8.3.18 Loopback Testing
      19. 8.3.19 BIST
      20. 8.3.20 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
      2. 8.4.2 High-Speed I/O Directly-Coupled Mode
      3. 8.4.3 High-Speed I/O AC-Coupled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7 High-Speed Data Output

The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-Ω impedance environment. The magnitude of the differential-pair signal swing is compatible with pseudo emitter coupled logic (PECL) levels when AC coupled. The line can be directly coupled or AC coupled. See Figure 13 and Figure 14 for termination details. The outputs also provide preemphasis to compensate for AC loss when driving a cable or PCB backplane trace over a long distance (see Figure 9). The level of preemphasis is controlled by PRE (see Table 2).

TLK2711-SP ov_prea_gls307_.gifFigure 9. Output Voltage Under Preemphasis (VTXP to VTXN)

Table 2. Programmable Preemphasis

PREPREEMPHASIS LEVEL (%)
VOD(P), VOD(D)(1)
0 5%
1 20%
(1) VOD(p): Voltage swing when there is a transition in the data stream.
VOD(d): Voltage swing when there is no transition in the data stream.