SGLS307P July 2006 – February 2018 TLK2711-SP
PRODUCTION DATA.
The parallel-to-serial shift register takes in the 20-bit-wide data word multiplexed from the two parallel 8-bit/10-bit encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the internally generated bit clock, which is 10× the TXCLK input frequency. The LSB (TXD0) is transmitted first.