SGLS307P July 2006 – February 2018 TLK2711-SP
PRODUCTION DATA.
The receive bus interface drives 16-bit-wide single-ended TTL parallel data at the RXD0 to RXD15 pins. Data is valid on the rising edge of the RXCLK. The RXCLK is used as the recovered word clock. The data, RKLSB, RKMSB, and clock signals are aligned as shown in Figure 10. Detailed timing information can be found in the TTL Output Switching Characteristics.