CPU0_VBUSM2AXI_EDC | 0 | 1 | Redundant |
CPU0_VBUSM2AXI_EDC | 1 | 12 | Parity |
CPU0_VBUSM2AXI_EDC | 2 | 4 | Parity |
CPU0_VBUSM2AXI_EDC | 3 | 12 | Parity |
CPU0_VBUSM2AXI_EDC | 4 | 23 | Parity |
CPU0_VBUSM2AXI_EDC | 5 | 1 | Parity |
CPU0_VBUSM2AXI_EDC | 6 | 10 | Parity |
CPU0_VBUSM2AXI_EDC | 7 | 2 | Parity |
CPU0_VBUSM2AXI_EDC | 8 | 3 | Parity |
CPU0_VBUSM2AXI_EDC | 9 | 1 | Parity |
CPU0_VBUSM2AXI_EDC | 10 | 2 | Parity |
CPU0_VBUSM2AXI_EDC | 11 | 2 | Parity |
CPU0_VBUSM2AXI_EDC | 12 | 1 | Parity |
CPU0_VBUSM2AXI_EDC | 13 | 1 | Parity |
CPU0_VBUSM2AXI_EDC | 14 | 1 | Parity |
CPU0_VBUSM2AXI_EDC | 15 | 3 | Parity |
CPU0_VBUSM2AXI_EDC | 16 | 4 | Parity |
CPU0_VBUSM2AXI_EDC | 17 | 2 | Parity |
CPU0_VBUSM2AXI_EDC | 18 | 2 | Parity |
CPU0_VBUSM2AXI_EDC | 19 | 2 | Parity |
CPU0_VBUSM2AXI_EDC | 20 | 1 | Redundant |
CPU0_VBUSM2AXI_EDC | 21 | 32 | EDC |
CPU0_VBUSM2AXI_EDC | 22 | 32 | EDC |
CPU0_VBUSM2AXI_EDC | 23 | 8 | Parity |
CPU0_VBUSM2AXI_EDC | 24 | 1 | Redundant |
CPU0_VBUSM2AXI_EDC | 25 | 1 | Redundant |
CPU0_VBUSM2AXI_EDC | 26 | 10 | Parity |
CPU0_VBUSM2AXI_EDC | 27 | 64 | Parity |
CPU0_VBUSM2AXI_EDC | 28 | 63 | Parity |
CPU0_VBUSM2AXI_EDC | 29 | 17 | Parity |
CPU0_VBUSM2AXI_EDC | 30 | 10 | Parity |
CPU0_VBUSM2AXI_EDC | 31 | 7 | Parity |
CPU0_VBUSM2AXI_EDC | 32 | 8 | Parity |
CPU0_VBUSM2AXI_EDC | 33 | 8 | Parity |
CPU0_VBUSM2AXI_EDC | 34 | 64 | Parity |
CPU0_VBUSM2AXI_EDC | 35 | 56 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 0 | 1 | Redundant |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 1 | 12 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 2 | 1 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 3 | 3 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 4 | 10 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 5 | 4 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 6 | 32 | EDC |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 7 | 32 | EDC |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 8 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 9 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 10 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 11 | 48 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 12 | 32 | EDC |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 13 | 32 | EDC |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 14 | 32 | EDC |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 15 | 32 | EDC |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 16 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 17 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 18 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 19 | 56 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 20 | 2 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 21 | 2 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 22 | 1 | Redundant |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 23 | 1 | Redundant |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 24 | 3 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 25 | 10 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 26 | 12 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 27 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 28 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 29 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 30 | 38 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 31 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 32 | 17 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 33 | 8 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 34 | 12 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 35 | 64 | Parity |
PULSAR_ULS_MEM_MST0_EDC_CTRL_0 | 36 | 20 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 0 | 1 | Redundant |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 1 | 1 | Redundant |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 2 | 3 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 3 | 32 | EDC |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 4 | 32 | EDC |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 5 | 4 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 6 | 1 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 7 | 1 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 8 | 1 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 9 | 2 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 10 | 14 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 11 | 1 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 12 | 36 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 13 | 10 | Parity |
PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0 | 14 | 4 | Parity |
SCRP_EDC | 0 | 11 | Parity |
SCRP_EDC | 1 | 1 | Redundant |
SCRP_EDC | 2 | 32 | EDC |
SCRP_EDC | 3 | 1 | Redundant |
SCRP_EDC | 4 | 8 | Parity |
SCRP_EDC | 5 | 4 | Redundant |
SCRP_EDC | 6 | 3 | Parity |
SCRP_EDC | 7 | 12 | Parity |
SCRP_EDC | 8 | 4 | Redundant |
SCRP_EDC | 9 | 12 | EDC |
SCRP_EDC | 10 | 2 | Parity |
SCRP_EDC | 11 | 32 | Parity |
SCRP_EDC | 12 | 4 | Parity |
SCRP_EDC | 13 | 3 | Parity |
SCRP_EDC | 14 | 12 | Parity |
SCRP_EDC | 15 | 4 | Parity |
SCRP_EDC | 16 | 1 | Redundant |
SCRP_EDC | 17 | 1 | Redundant |
SCRP_EDC | 18 | 32 | EDC |
SCRP_EDC | 19 | 1 | Parity |
SCRP_EDC | 20 | 32 | Parity |
SCRP_EDC | 21 | 4 | Parity |
SCRP_EDC | 22 | 3 | Parity |
SCRP_EDC | 23 | 12 | Parity |
SCRP_EDC | 24 | 4 | Parity |
SCRP_EDC | 25 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 0 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 1 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 2 | 1 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 3 | 4 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 4 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 5 | 1 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 6 | 4 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 7 | 4 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 8 | 2 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 9 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 10 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 11 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 12 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 13 | 10 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 14 | 12 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 15 | 4 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 16 | 4 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 17 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 18 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 19 | 12 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 20 | 4 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 21 | 12 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 22 | 4 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 23 | 10 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 24 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 25 | 12 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 26 | 4 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 27 | 12 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 28 | 4 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 29 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 30 | 4 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 31 | 4 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 32 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 33 | 5 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 34 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 35 | 5 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 36 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 37 | 1 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 38 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 39 | 4 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 40 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 41 | 5 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 42 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 43 | 5 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 44 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 45 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 46 | 8 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 47 | 7 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 48 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 49 | 4 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 50 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 51 | 26 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 52 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 53 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 54 | 26 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 55 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 56 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 57 | 26 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 58 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 59 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 60 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 61 | 26 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 62 | 32 | EDC |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 63 | 3 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 64 | 1 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 65 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 66 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 67 | 3 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 68 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 69 | 1 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 70 | 1 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 71 | 32 | EDC |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 72 | 1 | Redundant |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 73 | 1 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 74 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 75 | 10 | Parity |
PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC | 76 | 1 | Parity |
PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL | 0 | 1 | Redundant |
PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL | 1 | 32 | EDC |
PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL | 2 | 1 | Parity |
PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL | 3 | 10 | Parity |
PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL | 4 | 4 | Parity |
PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL | 5 | 3 | Parity |