The integrated 64-bit Arm Cortex-A53
subsystem (A53SS) supports the following main features:
- Full Arm®v8-A architecture
compliancy
- Advanced Single Instruction
Multiple Data (SIMD) and floating point extension (Arm® Neon™)
- Floating-Point Unit (FPU)
VFPv4
- Armv8 Cryptography
Extensions
- Arm General Interrupt
Controller (GICv3) architecture
- In-order pipeline with
symmetric dual-issue of most instructions
- 32KB program and 32KB data
Level 1 (L1) Cache
- Support for up to four timers
within each Cortex-A53 core
- Arm® CoreSight™ Debug and
Trace Architecture
- ECC protection for L1 data
cache and L2 Cache
- Parity protection for L1
Instruction Cache
- 128-bit wide, synchronous or
asynchronous VBUSM initiator interface
- Dedicated RTI windowed
watchdog timer per core
- Support for Big-Endian (BE)
and Little-Endian (LE) at core level
- Interface with Arm GIC-500
Interrupt Controller (SoC level, not part of A53SS)
- Advanced power management for
low power optimization