SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
When the DMA handler has completed its āNā CBASS0 accesses, write_count is assigned with āNā.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Start the channel | MCSPI_CHiCTRL[0] EN | 1 |
Wait until write_count = N | ||
Disable DMA write request | MCSPI_CHiCONF[14] DMAW | 0 |
Wait until last_transfer = TRUE | ||
Wait for end of transfer | MCSPI_CHiSTAT[2] EOT | =1 |
Stop the channel | MCSPI_CHiCTRL[0] EN | 0 |
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Read MCSPI_IRQSTATUS | MCSPI_IRQSTATUS | 0x- |
Write MCSPI_IRQSTATUS to reset channel status bits | MCSPI_IRQSTATUS[channel i bits] | 0b1111 |
IF: TXi_EMPTY AND write_count = N | ||
last_transfer = TRUE | ||
ENDIF |