SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Enable interrupt event | MAILBOX_IRQ_ENABLE_SET_j[0 + y*2] | 0x1 |
User (processor) can perform another task until interrupt occurs See Section 8.1.3.1.3.2 for interrupt handling in receiving mode |