Figure 12-177
shows the MMCSDi module block diagram (where i represents a valid instance of MMCSD in a domain).
Basic Blocks:
- MMCSD Host Controller: The MMCSD Host Controller is situated in the MMCSD Subsystem and provides accessibility to external MMC/SD/SDIO devices using a Programmed IO method or DMA data transfer method.
- UHS-I PHY: The integrated UHS-I PHY provides an interface between the MMCSD Host Controller and external MMC/SD/SDIO devices.
- MMCSDi Interface: The MMCSDi Interface includes all used interface pins (for more information, see Table 12-194).
- Host Port: Provides a
64-bit wide read/write interface between the device and the MMCSD Subsystem
internal SRAM.
- Target Port: Provides a
32-bit wide interface between the device and the MMCSD Subsystem and MMCSD Host
Controller parts.
- MMCSD Host Controller Registers: This block includes set of all MMCSD Host Controller registers.
- MMCSD Subsystem and PHY Registers: This block implements memory-mapped registers at the MMCSD Subsystem level and memory-mapped registers to control and program the MMCSD PHY.
- ECC Aggregator: The ECC Aggregator block facilitates aggregating and reporting
internal SRAM ECC errors (for more information, see ECC Support).
- Internal SRAM with ECC: The internal SRAM block is used for data storage during read/write transactions.
- DMA Controller: Manages the data transfer between the device memory and the MMCSD Subsystem internal SRAM.
- System Clocks: There are asynchronous relationship between the interface
(system) clock and functional clock (for more information, see MMCSD
Clocks).
- System Reset: The reset to the MMCSD Subsystem provides reset to the all MMCSD
Subsystem parts (for more information, see MMCSD Clocks).
- Interrupts: The MMCSD Subsystem sources one MMCSD Host Controller interrupt and
four ECC Aggregator interrupts (for more information, see MMCSD Hardware
Requests and Interrupt Requests).
For more information about all MMCSD registers,
see MMCSD Registers.
The MMCSD Host Controller can use a Programmed IO method (PIO) or DMA data transfer method to access external MMC/SD/SDIO devices.
The target port is used for device CPU access to the MMCSD Host
Controller register set. The MMCSD Host Controller register set provides the
communication between the device CPU and the MMCSD Host Controller. In PIO method
the device CPU transfers data using the MMCSD0_DATA_PORT / MMCSD1_DATA_PORT
register. The data flow from the device memory to the external MMC/SD/SDIO device
(and vice versa) is through the target port, the MMCSD0_DATA_PORT / MMCSD1_DATA_PORT register in the
MMCSD Host Controller, and the PHY.
The host port is used for connection to the DMA controller (for more
information about ADMA support, see Advanced DMA and MMCSD0_CAPABILITIES /
MMCSD1_CAPABILITIES register). In DMA data transfer method the DMA controller uses
the host port to transfer data
between the device memory and the MMCSD Subsystem internal SRAM. The other side of
the internal SRAM is connected to the MMCSD Host Controller. The data flow from the
device memory to the external MMC/SD/SDIO device (and vice versa) is through the host port, internal SRAM,
MMCSD Host Controller, and the PHY. The DMA controller manages the read/write
operations from/to the internal SRAM without device CPU intervention.