SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Commands arriving on LPT and HPT to the DDRSS0 carry the VBUSM priority whereas the DDR controller uses AXI priority. The VBUSM2AXI bridge has the following registers for flexible mapping of the VBUSM priority to DDR controllers's priority:
This allows the system to essentially create different classes of service based on the initiator (Route ID) and the priority of the commands.
Each thread has a set of corresponding Priority Map Registers to map the incoming priority on that thread to appropriate AXI proirity. The default values of these registers are such that inherently the HPT traffic will have higher priority than the LPT traffic inside the controller. However, these settings can be changed via software per system needs.
The controller performs command arbitration based on AXI priority and the state of the DDR device (openness of banks, etc.). Commands with higher priority will be given execution preference over commands with lower priority. However, due to the state of the DDR device (openness of banks, etc.), a command with higher priority may not be executed before a lower priority command. Therefore, transactions within a thread can be reordered. In addition, the controller does not have any information on the thread type of the transactions. Therefore, commands can also be reordered between thread types. However, at all times the controller maintains coherency across all commands within a given thread.