R5FSS0_CORE0 |
R5FSS0_CORE0_cti_0 |
R5FSS0_CORE0_intr_IN_175 |
R5FSS0_CORE0 |
R5FSS0_CORE0 interrupt request |
level |
R5FSS0_CORE0 |
R5FSS0_CORE0_ecc_corrected_level_0 |
ESM0_esm_lvl_event_IN_208 |
ESM0 |
R5FSS0_CORE0 interrupt request |
level |
R5FSS0_CORE0 |
R5FSS0_CORE0_ecc_uncorrected_level_0 |
ESM0_esm_lvl_event_IN_209 |
ESM0 |
R5FSS0_CORE0 interrupt request |
level |
R5FSS0_CORE0 |
R5FSS0_CORE0_exp_intr_0 |
ESM0_esm_lvl_event_IN_210 |
ESM0 |
R5FSS0_CORE0 interrupt request |
level |
R5FSS0_CORE0 |
R5FSS0_CORE0_exp_intr_0 |
R5FSS0_CORE0_intr_IN_4 |
R5FSS0_CORE0 |
R5FSS0_CORE0 interrupt request |
level |
R5FSS0_CORE0 |
R5FSS0_CORE0_pmu_0 |
R5FSS0_CORE0_intr_IN_94 |
R5FSS0_CORE0 |
R5FSS0_CORE0 interrupt request |
level |
R5FSS0_CORE0 |
R5FSS0_CORE0_valfiq_0 |
R5FSS0_CORE0_intr_IN_95 |
R5FSS0_CORE0 |
R5FSS0_CORE0 interrupt request |
level |
R5FSS0_CORE0 |
R5FSS0_CORE0_valirq_0 |
R5FSS0_CORE0_intr_IN_96 |
R5FSS0_CORE0 |
R5FSS0_CORE0 interrupt request |
level |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_cti_0 |
WKUP_R5FSS0_CORE0_intr_IN_175 |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0 interrupt request |
level |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_ecc_corrected_level_0 |
ESM0_esm_lvl_event_IN_30 |
ESM0 |
WKUP_R5FSS0_CORE0 interrupt request |
level |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_ecc_uncorrected_level_0 |
ESM0_esm_lvl_event_IN_91 |
ESM0 |
WKUP_R5FSS0_CORE0 interrupt request |
level |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_exp_intr_0 |
ESM0_esm_lvl_event_IN_124 |
ESM0 |
WKUP_R5FSS0_CORE0 interrupt request |
level |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_exp_intr_0 |
WKUP_R5FSS0_CORE0_intr_IN_4 |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0 interrupt request |
level |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_pmu_0 |
WKUP_R5FSS0_CORE0_intr_IN_58 |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0 interrupt request |
level |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_valfiq_0 |
WKUP_R5FSS0_CORE0_intr_IN_59 |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0 interrupt request |
level |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_valirq_0 |
WKUP_R5FSS0_CORE0_intr_IN_60 |
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0 interrupt request |
level |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_commrx_level_0_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_90 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_commtx_level_0_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_91 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_cti_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_175 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_exp_intr_0 |
WKUP_ESM0_esm_lvl_event_IN_30 |
WKUP_ESM0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_exp_intr_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_4 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_pmu_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_94 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_valfiq_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_95 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0_cpu0_valirq_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_96 |
MCU_R5FSS0_CORE0 |
MCU_R5FSS0_CORE0 interrupt request |
level |