SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The SoC level memory map is constructed using a 36b physical address and follows the guideline to put peripherals at 64KB aligned boundary. No virtual address is supported on the SoC level. However, A53 core can support virtual address internally. If software utilizes the address more than 36b, only the lower 36b is used for SoC level address decoding and the upper address bits will be ignored by the SoC. Not all the 36b memory regions are implemented. Any transactions hitting the unimplemented address range will be terminated and routed to null end point to avoid system hang. An interrupt will be asserted and the above transaction will be logged. All the SoC level peripherals and processors use the common SoC memory except the 32b only processors, such as the R5 core. For those processors and peripherals which natively only supports 32b physical address, the Region based Address Translation (RAT) module is used to remap the 32b address into the common 36b SoC address map.