SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The procedure in Table 12-288 configures the transmit frame synchronization generator of the MCASP module.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Select number of TDM slots per frame (2 - 32). Must be set to 0x2, in case of an I2S-transmission. For more details on frame-sync generator, refer to Section 12.5.2.4.2.3, Frame-Sync Generator. | MCASP_AFSXCTL[15-7] XMOD | 0x- |
Choose the transmit frame sync width -single bit/single word. For more details on frame-sync generator, refer to Section 12.5.2.4.2.3, Frame-Sync Generator. | MCASP_AFSXCTL[4] FXWID | 0x- |
Select start of transmit frame sync polarity - rising /falling edge. For more details on frame-sync generator, refer to Section 12.5.2.4.2.3, Frame-Sync Generator. | MCASP_AFSXCTL[0] FSXP | 0x- |
IF transmit frame sync - FS is internally generated | Software test condition | |
Select internally- generated transmit frame sync. For more details on frame-sync generator, refer to Section 12.5.2.4.2.3, Frame-Sync Generator. | MCASP_AFSXCTL[1] FSXM | 0b1 |
If MCASP transmitter is required to output internally generated frame, AFSX pin must be set as an output in step 10 of the sequence documented in the Table 12-286. This must NOT be done in current step because the frame control register - MCASP_AFSXCTL must be appropriately configured prior to AFSX pin outputting a frame sync to an external device. | MCASP_PDIR[28] AFSX | 0b1 |
ELSE | ||
Select externally- generated transmit frame sync. For more details on frame-sync generator, refer to Section 12.5.2.4.2.3, Frame-Sync Generator. | MCASP_AFSXCTL[1] FSXM | 0b0 |
Setup the AFSX pin as input | MCASP_PDIR[28] AFSX | 0b0 |