The digital filter averages and down-samples data from the modulator to provide the final data rate (rate reduction). The order of the digital filter affects the amount of data averaging and in turn, the time delay of the conversion (or filter latency). The FIR and sinc1 filter modes are zero latency providing the conversion result in single cycle. The higher order sinc filters (sinc2, 3, 4, 5) have more than one conversion latency and therefore require more conversion cycles to provide fully settled data. Tradeoffs can be made between 50-Hz and 60-Hz line cycle rejection verses conversion latency by selection of the sinc filter order. A higher order sinc filter increases the rejection of the 50-Hz and 60-Hz line cycles, but also increases the filter latency. Filter latency is an important consideration when multiplexing (scanning) through input channels. To make sure that conversions are settled after changing channels, start a new conversion for each channel using the START pin or start command. Note if the multiplexer is changed during ongoing conversions, the conversion is stopped and restarted at the time multiplexer register is changed.
Table 9-13 lists the filter latency after starting the first conversion. Note the conversion latency depends on the filter setting. The conversion latency is illustrated in Figure 9-39. Parameter td(STDR) shows the latency from start to conversion data ready (DRDY low). Note that settled data are provided, assuming the analog input is settled before the start condition. After the first conversion is completed (in continuous conversion mode), subsequent conversions occur at the nominal data rate. The latency values are for the programmable time-delay parameter set to off (DELAY[3:0] = 000).
|CONVERSION LATENCY(1) (ms)|
In addition, chop or IDAC rotation mode can reduce the conversion data rate depending on the time-delay parameter. The 50-Hz and 60-Hz filter response nulls are not altered by chop or IDAC rotation modes. Equation 21 shows the effective data rate with the DELAY parameter.
Table 9-14 shows the first conversion latency of ADC2. The filter latency is the elapsed time after sending the START2 command before the first conversion is ready.
|DATA RATE (SPS)||CONVERSION LATENCY (ms)|
If the input signal changes while the ADC is continuously converting, the output data are a mix of old and new data, as shown in Figure 9-40. The filter latency values for settled data (td(STDR)) with an input step change while continuously converting is shown in Table 9-15. The filter latency values listed in the table (td(STDR)) assume the analog input is settled before the start of the first whole conversion period.
|DIGITAL FILTER||FULLY SETTLED CONVERSION td(DRDR)|
(1 / DR)(1)