Stepper motors have a distinct relation between the winding current, back-EMF, and mechanical torque load of the motor, as shown in Figure 7-21. As motor load approaches the torque capability of the motor for a given winding current, the back-EMF will move in phase with the winding current. By detecting back-emf phase shift between rising and falling current quadrants of the motor current, the DRV8434S can detect a motor overload stall condition or an end-of-line travel.

Figure 7-21 Stall Detection by Monitoring Motor Back-EMF

The Stall Detection algorithm works only when the device is programmed to operate in the smart tune Ripple Control decay mode. The EN_STL bit has to be '1' to enable stall detection. Additionally, if any fault condition exists (UVLO, OCP, OL, OTSD etc.), stall detection will be disabled.

The algorithm compares the back-EMF between the rising and falling current quadrants by monitoring PWM off time and generates a value represented by the 12-bit register TRQ_COUNT. The comparison is done in such a way that the TRQ_COUNT value is practically independent of motor current, ambient temperature and supply voltage. Full step mode of operation is supported by this algorithm.

For a lightly loaded motor, the TRQ_COUNT will be a non-zero value. As the motor approaches stall condition, TRQ_COUNT will approach zero and can be used to detect stall condition. If at anytime TRQ_COUNT falls below the stall threshold (represented by the 12-bit STALL_TH register), the device will detect a stall and the STALL, STL and FAULT bits are latched high in the SPI register. To indicate stall detection fault on the nFAULT pin, the STL_REP bit must be '1'. When the STL_REP bit is '1', the nFAULT pin will be driven low when a stall is detected.

In the stalled condition, the motor shaft does not spin. The motor starts to spin again when the stall condition is removed and the motor ramps to its target speed. The nFAULT is released and the fault registers are cleared when a clear faults command is issued either via the CLR_FLT bit or an nSLEEP reset pulse.

TRQ_COUNT is calculated as an average torque count of the most recent four electrical half-cycles of a spinning motor. The calculated value is updated in the device CTRL8 and CTRL9 registers within the next 100 ns. The registers are unchanged until the next update. Subsequent updates happen every electrical half-cycle.

High motor coil resistance can result in low TRQ_COUNT. The TRQ_SCALE bit allows scaling up low TRQ_COUNT values, for ease of further processing. If the initially calculated TRQ_COUNT value is less than 500 and the TRQ_SCALE bit is '1', then the TRQ_COUNT is multiplied by a factor of 8. If the TRQ_SCALE bit is '0', TRQ_COUNT retains the value originally calculated by the algorithm.

Stall threshold can be set in two ways – either the user can write the STALL_TH bits, or let the algorithm learn the stall threshold value using the stall learning process. The stall learning process is started by setting the STL_LRN bit to '1'. The motor is intentionally stalled briefly to allow the algorithm to learn the ideal stall threshold. At the end of a successful learning, the STALL_TH register is updated with the learnt stall threshold value. The STL_LRN_OK bit goes high after a successful learning.

A stall threshold learnt at one speed may not work well for another speed. It is recommended to re-learn the stall threshold every time the motor speed is changed considerably.