SLASFC6 Data sheet

SLASFC6A August 2024 – August 2025 TAS2120

PRODUCTION DATA

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Mechanical Data (Package|Pins)

RBG|26
- MPQF809

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7.1 PAGE 0 Registers

Table 7-1 lists the memory-mapped registers for the PAGE 0 registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 PAGE 0 Registers

Address	Acronym	Description	Section
0h	Page	Device Page	Section 7.1.1
1h	SW_RESET	Software Reset	Section 7.1.2
2h	PWR_CTL	Power Control	Section 7.1.3
3h	DEVICE_CFG_01	Device configuration registers	Section 7.1.4
4h	DEVICE_CFG_02	Device configuration registers	Section 7.1.5
5h	DEVICE_CFG_03	Device configuration registers	Section 7.1.6
6h	DEVICE_CFG_04	Device configuration registers	Section 7.1.7
7h	DEVICE_CFG_05	Device configuration registers	Section 7.1.8
8h	TDM_CFG1	TDM Configuration registers	Section 7.1.9
9h	TDM_CFG2	TDM Configuration registers	Section 7.1.10
Ah	TDM_CFG3	TDM Configuration registers	Section 7.1.11
Ch	TDM_CFG5	TDM Configuration registers	Section 7.1.12
Fh	TDM_CFG8	TDM Configuration registers	Section 7.1.13
10h	TDM_CFG9	TDM Configuration registers	Section 7.1.14
11h	TDM_CFG10	TDM Configuration registers	Section 7.1.15
12h	TDM_CFG11	TDM Configuration registers	Section 7.1.16
13h	TDM_CFG12	TDM Configuration registers	Section 7.1.17
14h	TDM_DET	TDM Clock detection monitor	Section 7.1.18
15h	MONITOR_CFG_01	Monitoring Configuration	Section 7.1.19
17h	LIM_CFG_0	Limiter configuration	Section 7.1.20
18h	BOP_CFG_0	Brown out protection configuration	Section 7.1.21
1Ch	IO_CFG_02	IO Configuration	Section 7.1.22
1Dh	IO_CFG_03	IO Configuration	Section 7.1.23
1Eh	NG_CFG0	Noise Gate Controls	Section 7.1.24
21h	BST_CFG_01	Boost Configuration	Section 7.1.25
22h	BST_CFG_02	Boost Configuration	Section 7.1.26
24h	BST_CFG_03	Boost Configuration	Section 7.1.27
25h	INTERRUPT_CFG1	IRQZ clear	Section 7.1.28
26h	SAR_MONITOR_01	VBAT Monitor MSB	Section 7.1.29
27h	SAR_MONITOR_02	VBAT Monitor MSB	Section 7.1.30
28h	SAR_MONITOR_03	PVDD Monitor MSB	Section 7.1.31
29h	SAR_MONITOR_04	PVDD Monitor MSB	Section 7.1.32
2Ah	SAR_MONITOR_06	Temperature monitor	Section 7.1.33
31h	CLASSD_CFG_01	ClassD amp configurations	Section 7.1.34
32h	CLASSD_CFG_02	ClassD amp configurations	Section 7.1.35
3Bh	BST_CFG_05	Boost Configuration	Section 7.1.36
3Ch	THERM_CFG	Thermal warning configuration	Section 7.1.37
5Bh	INT_MASK_0	Interrupt Masks	Section 7.1.38
5Ch	INT_MASK_1	Interrupt Masks	Section 7.1.39
5Dh	INT_MASK_2	Interrupt Masks	Section 7.1.40
5Eh	INT_MASK_3	Interrupt Masks	Section 7.1.41
5Fh	INT_MASK_4	Interrupt Masks	Section 7.1.42
60h	INT_LATCH_0	Latched interrupt readback	Section 7.1.43
61h	INT_LATCH_1	Latched interrupt readback	Section 7.1.44
62h	INT_LATCH_2	Latched interrupt readback	Section 7.1.45
63h	INT_LATCH_3	Latched interrupt readback	Section 7.1.46
64h	INT_LATCH_4	Latched interrupt readback	Section 7.1.47
65h	NG_IDLE_STATUS	Latched interrupt readback	Section 7.1.48
78h	REV_ID	Revision ID	Section 7.1.49
7Fh	BOOK	Device Book	Section 7.1.50

7.1.1 Page Register (Address = 0h) [Reset = 00h]

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The device's memory map is divided into pages and books. This register sets the page.

Table 7-2 Page Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PAGE[7:0]	R/W	0h	Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255

7.1.2 SW_RESET Register (Address = 1h) [Reset = 00h]

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Asserting Software Reset will place all register values in their default POR (Power on Reset) state.

Table 7-3 SW_RESET Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0h	Reserved
0	SW_RESET	R/W	0h	Software reset. Bit is self clearing. 0h = Don't reset 1h = Reset

7.1.3 PWR_CTL Register (Address = 2h) [Reset = 03h]

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Sets device's mode of operation and Power Configuration.

Table 7-4 PWR_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	MODE[1:0]	R/W	3h	Device operational mode. 0h = Active 1h = Reserved 2h = Software Shutdown 3h = Wake-up and Shutdown on ASI Clock

7.1.4 DEVICE_CFG_01 Register (Address = 3h) [Reset = 81h]

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This register configures various device modes.

Table 7-5 DEVICE_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	EFFICIENCY_MODE[1:0]	R/W	2h	Device operational mode. 0h = Music Efficiency and Noise Gate mode disabled 1h = Noise Gate Mode Only 2h = Music Efficiency Only 3h = Music Efficiency and Noise Gate mode
5-2	RESERVED	R	0h	Reserved
1-0	SDZ_MODE[1:0]	R/W	1h	SDZ Mode configuration. 0h = Soft shutdown and device reset 1h = Immediate shutdown and device reset 2h = Soft shutdown only 3h = Reserved

7.1.5 DEVICE_CFG_02 Register (Address = 4h) [Reset = 8Ch]

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This register configures various device modes.

Table 7-6 DEVICE_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	I2C_GBL_EN	R/W	1h	I2C global address. 0h = Disabled 1h = Enabled
6	RESERVED	R/W	0h	Reserved
5-3	CLK_HALT_TIME[2:0]	R/W	1h	Pre-power-up valid clock checking time duration. 0h = Disabled (infinite time) 1h = 800 us 2h = 3.2 ms 3h = 34.1 ms 4h = 68.3 ms 5h = 256 ms 6h = 768 ms 7h = 1.3 s
2	CLK_BASED_PWR_UP	R/W	1h	Clock error detection enable/disable. 0h = Disable 1h = Enabled
1	RESERVED	R/W	0h	Reserved
0	RESERVED	R/W	0h	Reserved

7.1.6 DEVICE_CFG_03 Register (Address = 5h) [Reset = 00h]

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This register configures various device modes.

Table 7-7 DEVICE_CFG_03 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	OTE_RETRY	R/W	0h	Retry after over temperature event. 0h = Do not retry 1h = Retry after "RETRY_WAIT_TIME"
3	RESERVED	R/W	0h	Reserved
2	CLKE_RETRY	R/W	0h	Retry after Internal Clock Error event. 0h = Do not retry 1h = Retry after "RETRY_WAIT_TIME"
1	RESERVED	R/W	0h	Reserved
0	RESERVED	R/W	0h	Reserved

7.1.7 DEVICE_CFG_04 Register (Address = 6h) [Reset = 04h]

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This register configures various device modes.

Table 7-8 DEVICE_CFG_04 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	Reserved
5-4	SEL_VBAT_MODE[1:0]	R/W	0h	Selects VBAT mode of operation. 0h = VBAT 1S mode, supply sense on VBAT 1h = VBAT 1S mode, supply sense on VBAT_SNS 2h = VBAT 2S mode, supply sense on VBAT_SNS 3h = RESERVED
3-2	IRQZ_PIN_CFG[1:0]	R/W	1h	IRQZ interrupt configuration. IRQZ will assert. 0h = Reserved 1h = on any unmasked latched interrupts 2h = Reserved 3h = for 2-4ms every 4ms on any unmasked latched interrupts
1	RESERVED	R	0h	Reserved
0	RETRY_WAIT_TIME	R/W	0h	Retry wait time after device detects error (Valid only for errors with retry options available). 0h = 1.5 sec 1h = 100ms

7.1.8 DEVICE_CFG_05 Register (Address = 7h) [Reset = 00h]

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This register configures various device modes.

Table 7-9 DEVICE_CFG_05 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	SAMPLE_RATE_CFG	R/W	0h	Sampling Rate selection. 0h = Audio data rate is multiple/sub-multiple of 48 Ksps 1h = Audio data rate is multiple/sub-multiple of 44.1 Ksps
5-0	AMP_LVL[5:0]	R/W	0h	Device Channel Gain setting 0h = 21.000dB 1h = 20.498dB 2h = 19.997dB 3h = 19.495dB 4h = 18.993dB 26h = 1.935dB 27h = 1.434dB 28h = 0.932dB 29h = 0.430dB 2Ah = -0.071dB

7.1.9 TDM_CFG1 Register (Address = 8h) [Reset = 82h]

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This register configures device TDM modes.

Table 7-10 TDM_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FRAME_START	R/W	1h	TDM frame start polarity. 0h = Low to High on FSYNC 1h = High to Low on FSYNC
6	RX_JUSTIFY	R/W	0h	TDM RX sample justification within the time slot. 0h = Left 1h = Right
5-1	RX_OFFSET[4:0]	R/W	1h	TDM RX start of frame to time slot 0 offset (SBCLK cycles).
0	RX_EDGE	R/W	0h	TDM RX capture clock polarity. 0h = Rising edge of SBCLK 1h = Falling edge of SBCLK

7.1.10 TDM_CFG2 Register (Address = 9h) [Reset = 0Ah]

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This register configures device TDM modes.

Table 7-11 TDM_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	0h	Reserved
5-4	RX_SCFG[1:0]	R/W	0h	TDM RX time slot select config. 0h = Mono with time slot equal to I2C address offset 1h = Mono left channel 2h = Mono right channel 3h = Stereo downmix (L+R)/2
3-2	RX_WLEN[1:0]	R/W	2h	TDM RX word length. 0h = 16 bits 1h = 20 bits 2h = 24 bits 3h = 32 bits
1-0	RX_SLEN[1:0]	R/W	2h	TDM RX time slot length. 0h = 16 bits 1h = 24 bits 2h = 32 bits 3h = Reserved

7.1.11 TDM_CFG3 Register (Address = Ah) [Reset = 10h]

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This register configures device TDM modes.

Table 7-12 TDM_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RX_SLOT_R[3:0]	R/W	1h	TDM RX Right Audio Channel Time Slot.
3-0	RX_SLOT_L[3:0]	R/W	0h	TDM RX Left Audio Channel Time Slot.

7.1.12 TDM_CFG5 Register (Address = Ch) [Reset = 13h]

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This register configures device TDM modes.

Table 7-13 TDM_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TX_KEEPCY	R/W	0h	TDM TX SDOUT LSB data will be driven for 0h = full-cycle 1h = half-cycle
6	TX_KEEPLN	R/W	0h	TDM TX SDOUT will hold the bus for the following when TX_KEEPEN is enabled 0h = 1 LSB cycle 1h = always
5	TX_KEEPEN	R/W	0h	TDM TX SDOUT bus keeper enable. 0h = Disable bus keeper 1h = Enable bus keeper
4	TX_FILL	R/W	1h	TDM TX SDOUT unused bitfield fill. 0h = Transmit 0 1h = Transmit Hi-Z
3-1	TX_OFFSET[2:0]	R/W	1h	TDM TX start of frame to time slot 0 offset.
0	TX_EDGE	R/W	1h	TDM TX launch clock polarity. 0h = Rising edge of SBCLK 1h = Falling edge of SBCLK

7.1.13 TDM_CFG8 Register (Address = Fh) [Reset = 04h]

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This register configures device TDM modes.

Table 7-14 TDM_CFG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VBAT_SLEN	R/W	0h	TDM TX VBAT time slot length. 0h = Truncate to 8-bits 1h = Left justify to 16-bits
6	VBAT_TX	R/W	0h	TDM TX VBAT transmit enable. 0h = Disabled 1h = Enabled
5-0	VBAT_SLOT[5:0]	R/W	4h	TDM TX VBAT time slot.

7.1.14 TDM_CFG9 Register (Address = 10h) [Reset = 05h]

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This register configures device TDM modes.

Table 7-15 TDM_CFG9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	TEMP_TX	R/W	0h	TDM TX temp sensor transmit enable. 0h = Disabled 1h = Enabled
5-0	TEMP_SLOT[5:0]	R/W	5h	TDM TX temp sensor time slot.

7.1.15 TDM_CFG10 Register (Address = 11h) [Reset = 07h]

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This register configures device TDM modes

Table 7-16 TDM_CFG10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	STATUS_TX	R/W	0h	TDM TX status bits transmit enable. 0h = Disabled 1h = Enabled
5-0	STATUS_SLOT[5:0]	R/W	7h	TDM TX status bits time slot.

7.1.16 TDM_CFG11 Register (Address = 12h) [Reset = 06h]

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This register configures device TDM modes.

Table 7-17 TDM_CFG11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PVDD_SLEN	R/W	0h	TDM TX PVDD time slot length. 0h = Truncate to 8-bits 1h = Left justify to 16-bits
6	PVDD_TX	R/W	0h	TDM TX PVDD transmit enable. 0h = Disabled 1h = Enabled
5-0	PVDD_SLOT[5:0]	R/W	6h	TDM TX PVDD time slot.

7.1.17 TDM_CFG12 Register (Address = 13h) [Reset = 12h]

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This register configures device TDM modes.

Table 7-18 TDM_CFG12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	AUDIO_SLEN	R/W	0h	TDM audio slot length 0h = 16-bits 1h = 24-bits
6	AUDIO_TX	R/W	0h	TDM audio output transmit is 0h = Disabled 1h = Enabled
5-0	AUDIO_SLOT[5:0]	R/W	12h	TDM TX status time slot.

7.1.18 TDM_DET Register (Address = 14h) [Reset = 7Fh]

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Readback of internal auto clock detection.

Table 7-19 TDM_DET Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6-3	FS_RATIO_DETECTED[3:0]	R	Fh	Detected SBCLK to FSYNC ratio. 0h = 16 1h = 24 2h = 32 3h = 48 4h = 64 5h = 96 6h = 128 7h = 192 8h = 256 9h = 384 Ah = 512 Bh = 250 Dh = 500 Eh = Reserved Fh = Invalid ratio
2-0	FS_RATE_DETECTED[2:0]	R	7h	Detected sample rate of TDM bus. 0h = Reserved 1h = 14.7/16 KHz 2h = 22.05/24 KHz 3h = 29.4/32 KHz 4h = 44.1/48 KHz 5h = 88.2/96 kHz 6h = 176.4/192 kHz 7h = Error condition

7.1.19 MONITOR_CFG_01 Register (Address = 15h) [Reset = 00h]

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This register configures the Monitor channels of the device.

Table 7-20 MONITOR_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SUPPLY_SAMPLING_RATE	R/W	0h	Configure VBAT and PVDD sampling rates 0h = VBAT Sampling rate is higher than PVDD 1h = PVDD Sampling rate is higher than VBAT
6-0	RESERVED	R	0h	Reserved

7.1.20 LIM_CFG_0 Register (Address = 17h) [Reset = 00h]

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This register configures the voltage limiter module.

Table 7-21 LIM_CFG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	LIM_MODE[1:0]	R/W	0h	Limiter enable. 0h = Disabled 1h = VBAT voltage based limiter mode 2h = PVDD voltage based limiter mode 3h = RESERVED
5	SUPPLY_HEADROOM_LIM_MODE	R/W	0h	Select limiter threshold based on supply headroom. 0h = Disabled 1h = Enabled
4-0	RESERVED	R	0h	Reserved

7.1.21 BOP_CFG_0 Register (Address = 18h) [Reset = 00h]

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This register configures brown out protection module.

Table 7-22 BOP_CFG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R	0h	Reserved
4	BOP_SRC	R/W	0h	Brown out prevention Source control 0h = VBAT 1h = PVDD
3	BOPSD_EN	R/W	0h	Brown out prevention shutdown enable. 0h = Disabled 1h = Enabled
2	BOP_HLD_CLR	R/W	0h	BOP infinite hold clear (self clearing). Available when BOP_INF_HLD = 1 0h = Don't clear 1h = Clear
1	BOP_INF_HLD	R/W	0h	Infinite hold on brown out event. 0h = Use BOP_HLD_TM after brown out event 1h = Don't release until BOP_HLD_CLR is asserted high
0	BOP_EN	R/W	0h	Brown out prevention (BOP) enable. 0h = Disabled 1h = Enabled

7.1.22 IO_CFG_02 Register (Address = 1Ch) [Reset = 3Fh]

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This register configures the IO buffers.

Table 7-23 IO_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IRQZ_POL	R/W	0h	IRQZ pin polarity for interrupt. 0h = Active Low 1h = Active High
6	RESERVED	R	0h	Reserved
5	RESERVED	R/W	1h	Reserved
4	IRQZ_PD	R/W	1h	Weak pull down for IRQZ. 0h = Disabled 1h = Enabled
3	RESERVED	R/W	1h	Reserved
2	RESERVED	R/W	1h	Reserved
1	SDZ_PD	R/W	1h	Weak pull down for SDZ. 0h = Disabled 1h = Enabled
0	SDA_PD	R/W	1h	Weak pull down for SDA. 0h = Disabled 1h = Enabled

7.1.23 IO_CFG_03 Register (Address = 1Dh) [Reset = F0h]

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This register configures the IO buffers.

Table 7-24 IO_CFG_03 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADR_PD	R/W	1h	Weak pull down for ADR. 0h = Disabled 1h = Enabled
6	SDZ_PD	R/W	1h	Weak pull down for SDZ. 0h = Disabled 1h = Enabled
5	RESERVED	R/W	1h	Reserved
4	CLH_PD	R/W	1h	Weak pull down for CLH. 0h = Disabled 1h = Enabled
3	SDOUT_PD	R/W	0h	Weak pull down for SDOUT. 0h = Disabled 1h = Enabled
2	SDIN_PD	R/W	0h	Weak pull down for SDIN. 0h = Disabled 1h = Enabled
1	FSYNC_PD	R/W	0h	Weak pull down for FSYNC. 0h = Disabled 1h = Enabled
0	SBCLK_PD	R/W	0h	Weak pull down for SBCLK. 0h = Disabled 1h = Enabled

7.1.24 NG_CFG0 Register (Address = 1Eh) [Reset = 60h]

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Noise gate hysteresis, threshold level, and enable.

Table 7-25 NG_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	NG_HYST_TIMER[1:0]	R/W	1h	Noise Gate Entry hysteris timer. 0h = 10ms 1h = 50ms 2h = 100ms 3h = 1000ms
5-3	NG_TH_LVL[2:0]	R/W	4h	Noise-gate audio threshold level. 0h = -85 dBFS 1h = -90 dBFS 2h = -95 dBFS 3h = -100 dBFS 4h = -105 dBFS 5h = -110 dBFS 6h = -115 dBFS 7h = -120 dBFS
2-0	RESERVED	R	0h	Reserved

7.1.25 BST_CFG_01 Register (Address = 21h) [Reset = 10h]

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This register configures internal Boost controller.

Table 7-26 BST_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R	0h	Reserved
4	BOOST_PHASE_SYNC_EN	R/W	1h	Boost Phase sync enable. 0h = Disabled 1h = Enabled
3-2	BOOST_PHASE[1:0]	R/W	0h	Boost Phase sync delay control, applicable only when boost_phase_sync_en = 1 0h = Phase shift is 0ns 1h = Phase shift is 65ns 2h = Phase shift is 130ns 3h = Phase shift is 195ns
1	BOOST_PHASE_FROM_ADDRESS_PIN	R/W	0h	Boost Phase shift sync control selected automatically based on i2c target address detected from Address pin. Applicable only when boost_phase_sync_en = 1 0h = Disabled 1h = Enabled
0	RESERVED	R/W	0h	Reserved

7.1.26 BST_CFG_02 Register (Address = 22h) [Reset = 23h]

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This register configures internal Boost controller.

Table 7-27 BST_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	BST_MODE[1:0]	R/W	0h	Boost Mode. 0h = Class-H 1h = Class-G 2h = Always ON 3h = Always OFF (Passthrough)
5	BST_EN	R/W	1h	Boost enable. 0h = Disabled (External PVDD mode) 1h = Enabled
4-3	BST_MIN_FREQ_SEL[1:0]	R/W	0h	Boost active mode PFM lower limit. 0h = No Limit 1h = 25 kHz 2h = 50 kHz 3h = RESERVED
2-1	RESERVED	R/W	1h	Reserved
0	RESERVED	R/W	1h	Reserved

7.1.27 BST_CFG_03 Register (Address = 24h) [Reset = 48h]

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This register configures Boost controller.

Table 7-28 BST_CFG_03 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	2h	Reserved
4-3	RESERVED	R/W	1h	Reserved
2	RESERVED	R/W	0h	Reserved
1	External_boost_classh_en	R/W	0h	Support for external_boost PWM control 0h = Disabled 1h = Enabled
0	Sel_pwm_out_polarity	R/W	0h	External_boost PWM control polarity 0h = Default 1h = Inverted

7.1.28 INTERRUPT_CFG1 Register (Address = 25h) [Reset = 00h]

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This register clears all the latched interrupt registers.

Table 7-29 INTERRUPT_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	Shared_boost_primary_en	R/W	0h	Primary device control in shared boost mode 0h = Disabled 1h = Enabled
6	Shared_boost_secondary_en	R/W	0h	Secondary device control in shared boost mode 0h = Disabled 1h = Enabled
5-2	RESERVED	R	0h	Reserved
1	INT_CLR_LTCH	R/W	0h	Clear INT_LTCH registers. 0h = Don't clear 1h = Clear
0	RESERVED	R	0h	Reserved

7.1.29 SAR_MONITOR_01 Register (Address = 26h) [Reset = 00h]

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This register provides sensed VBAT Voltage.

Table 7-30 SAR_MONITOR_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VBAT_CNV_MSB[7:0]	R	0h	Returns the SAR ADC VBAT monitored voltage MSBs. VBAT value converted is based on selection of SEL_VBAT_MODE

7.1.30 SAR_MONITOR_02 Register (Address = 27h) [Reset = 00h]

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This register provides sensed VBAT Voltage.

Table 7-31 SAR_MONITOR_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	VBAT_CNV_LSB[3:0]	R	0h	Returns the SAR ADC VBAT monitored voltage LSBs. VBAT value converted is based on selection of SEL_VBAT_MODE
3-0	RESERVED	R	0h	Reserved

7.1.31 SAR_MONITOR_03 Register (Address = 28h) [Reset = 00h]

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This register provides sensed VBAT Voltage.

Table 7-32 SAR_MONITOR_03 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PVDD_CNV_MSB[7:0]	R	0h	Returns the SAR ADC PVDD monitored voltage MSBs.

7.1.32 SAR_MONITOR_04 Register (Address = 29h) [Reset = 00h]

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This register provides sensed VBAT Voltage.

Table 7-33 SAR_MONITOR_04 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	PVDD_CNV_LSB[3:0]	R	0h	Returns the SAR ADC PVDD monitored voltage LSBs.
3-0	RESERVED	R	0h	Reserved

7.1.33 SAR_MONITOR_06 Register (Address = 2Ah) [Reset = 00h]

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This register provides sensed temperature.

Table 7-34 SAR_MONITOR_06 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	TMP_CNV[7:0]	R	0h	Returns the SAR ADC Temperature monitored data.

7.1.34 CLASSD_CFG_01 Register (Address = 31h) [Reset = 04h]

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This register configures the class-D amplifier.

Table 7-35 CLASSD_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	0h	Reserved
5-4	CLASSD_OUTPUT_EDGERATE_CTRL[1:0]	R/W	0h	Edgerate programmability control. 0h = Class-D output edge rate of approximately 0.5 V/ns 1h = Class-D output edge rate of approximately 1 V/ns 2h = Reserved 3h = Class-D output edge rate of approximately 2 V/ns
3	CLASSD_HIZ_MODE	R/W	0h	Amp output state in Noise gate mode (0 = Not Hi-Z, 1 = Hi-Z) 0h = Disabled 1h = Enabled
2	RESERVED	R/W	1h	Reserved
1-0	RESERVED	R	0h	Reserved

7.1.35 CLASSD_CFG_02 Register (Address = 32h) [Reset = 9Ch]

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This register configures the class-D amplifier.

Table 7-36 CLASSD_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EN_Y_BRIDGE_MODE	R/W	1h	Enable/Disable VDD Bridge mode during device operation 0h = VDD Bridge mode disabled 1h = VDD Bridge mode enabled
6	RESERVED	R/W	0h	Reserved
5-4	RESERVED	R/W	1h	Reserved
3-2	Ybridge_hyst_timer[1:0]	R/W	3h	Time hysteresis programability 0h = 100 us 1h = 500 us 2h = 5 ms 3h = 50 ms
1-0	RESERVED	R	0h	Reserved

7.1.36 BST_CFG_05 Register (Address = 3Bh) [Reset = E3h]

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This register configures internal Boost controller.

Table 7-37 BST_CFG_05 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VBOOST_MAX_CTRL[7:0]	R/W	E3h	Boost VMAX setting in class-H mode. 54h = 5.54V (Min setting) E5h = 15.11V (Max setting)

7.1.37 THERM_CFG Register (Address = 3Ch) [Reset = 00h]

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This register configures thermal warning detection.

Table 7-38 THERM_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0h	Reserved
0	EN_THERM_WARN_DET	R/W	0h	Enable control for thermal warning detection feature. 0h = Disabled 1h = Enabled

7.1.38 INT_MASK_0 Register (Address = 5Bh) [Reset = 03h]

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This register configures Masks for Interrupt flags.

Table 7-39 INT_MASK_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK0[7]	R/W	0h	Mask for Interrupt due to BOP Inf Hold flag. 0h = Don't Mask 1h = Mask
6	INT_MASK0[6]	R/W	0h	Mask for Interrupt due to limiter attentuation flag. 0h = Don't Mask 1h = Mask
5	INT_MASK0[5]	R/W	0h	Mask for Interrupt due to supply less than inf pt flag. 0h = Don't Mask 1h = Mask
4	INT_MASK0[4]	R/W	0h	Mask for Interrupt due to limiter active flag. 0h = Don't Mask 1h = Mask
3	INT_MASK0[3]	R/W	0h	Mask for Interrupt due to brownout detected flag. 0h = Don't Mask 1h = Mask
2	INT_MASK0[2]	R/W	0h	Mask for Interrupt due to bop active flag. 0h = Don't Mask 1h = Mask
1	INT_MASK0[1]	R/W	1h	Mask for Interrupt due to device active flag. 0h = Don't Mask 1h = Mask
0	RESERVED	R/W	1h	Reserved

7.1.39 INT_MASK_1 Register (Address = 5Ch) [Reset = 1Fh]

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This register configures Masks for Interrupt flags.

Table 7-40 INT_MASK_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK1[7]	R/W	0h	Mask for Interrupt due to PVDD Under voltage. 0h = Don't Mask 1h = Mask
6	INT_MASK1[6]	R/W	0h	Mask for Interrupt due to VBAT 2S supply under voltage. 0h = Don't Mask 1h = Mask
5	RESERVED	R/W	0h	Reserved
4	INT_MASK1[4]	R/W	1h	Mask for Interrupt due to Thermal Warning 135C 0h = Don't Mask 1h = Mask
3	INT_MASK1[3]	R/W	1h	Mask for Interrupt due to Thermal Warning 125C 0h = Don't Mask 1h = Mask
2	INT_MASK1[2]	R/W	1h	Mask for Interrupt due to Thermal Warning 115C 0h = Don't Mask 1h = Mask
1	INT_MASK1[1]	R/W	1h	Mask for Interrupt due to Thermal Warning 105C 0h = Don't Mask 1h = Mask
0	RESERVED	R/W	1h	Reserved

7.1.40 INT_MASK_2 Register (Address = 5Dh) [Reset = 2Fh]

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This register configures Masks for Interrupt flags.

Table 7-41 INT_MASK_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK2[7]	R/W	0h	Mask for Interrupt due to watchdog expiry 0h = Don't Mask 1h = Mask
6	RESERVED	R/W	0h	Reserved
5	INT_MASK2[5]	R/W	1h	Mask for Interrupt due to frame out of sync 0h = Don't Mask 1h = Mask
4	INT_MASK2[4]	R/W	0h	Mask for Interrupt due to PLL clock error 0h = Don't Mask 1h = Mask
3	INT_MASK2[3]	R/W	1h	Mask for Interrupt due to tdm error 0h = Don't Mask 1h = Mask
2	INT_MASK2[2]	R/W	1h	Mask for Interrupt due to ratio change error flag 0h = Don't Mask 1h = Mask
1	INT_MASK2[1]	R/W	1h	Mask for Interrupt due to fs change error flag 0h = Don't Mask 1h = Mask
0	INT_MASK2[0]	R/W	1h	Mask for Interrupt due to invalid ratio fs flag 0h = Don't Mask 1h = Mask

7.1.41 INT_MASK_3 Register (Address = 5Eh) [Reset = 10h]

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This register configures Masks for Interrupt flags.

Table 7-42 INT_MASK_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK3[7]	R/W	0h	Mask for Interrupt due to over temperature detected 0h = Don't Mask 1h = Mask
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	RESERVED	R/W	1h	Reserved
3	INT_MASK3[3]	R/W	0h	Mask for Interrupt due to Class-D Over current protection 0h = Don't Mask 1h = Mask
2	INT_MASK3[2]	R/W	0h	Mask for Interrupt due to pvdd_ov_flag 0h = Don't Mask 1h = Mask
1	RESERVED	R/W	0h	Reserved
0	RESERVED	R/W	0h	Reserved

7.1.42 INT_MASK_4 Register (Address = 5Fh) [Reset = 0Ah]

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This register configures Masks for Interrupt flags.

Table 7-43 INT_MASK_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK4[7]	R/W	0h	Mask for Interrupt due to vbat_por 0h = Don't Mask 1h = Mask
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	1h	Reserved
2	INT_MASK4[2]	R/W	0h	Mask for Interrupt due to clock halt flag. This interrupt also flags errors due to Pre-power-up clock error while using Wake-up-on-ASI feature 0h = Don't Mask 1h = Mask
1	RESERVED	R/W	1h	Reserved
0	RESERVED	R/W	0h	Reserved

7.1.43 INT_LATCH_0 Register (Address = 60h) [Reset = 00h]

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This register provides the status of latched interrupts.

Table 7-44 INT_LATCH_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH0[7]	R	0h	Interrupt due to BOP Inf Hold flag 0h = No interrupt 1h = Interrupt
6	INT_LTCH0[6]	R	0h	Interrupt due to limiter attentuation flag 0h = No interrupt 1h = Interrupt
5	INT_LTCH0[5]	R	0h	Interrupt due to supply less than inf pt flag 0h = No interrupt 1h = Interrupt
4	INT_LTCH0[4]	R	0h	Interrupt due to limiter active flag 0h = No interrupt 1h = Interrupt
3	INT_LTCH0[3]	R	0h	Interrupt due to brownout detected flag 0h = No interrupt 1h = Interrupt
2	INT_LTCH0[2]	R	0h	Interrupt due to bop active flag 0h = No interrupt 1h = Interrupt
1	INT_LTCH0[1]	R	0h	Live Interrupt due to device active flag 0h = No interrupt 1h = Interrupt
0	RESERVED	R	0h	Reserved

7.1.44 INT_LATCH_1 Register (Address = 61h) [Reset = 00h]

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This register provides the status of latched interrupts.

Table 7-45 INT_LATCH_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH1[7]	R	0h	Interrupt due to PVDD under voltage detection 0h = No interrupt 1h = Interrupt
6	INT_LTCH1[6]	R	0h	Interrupt due to VBAT2S under voltage detection 0h = No interrupt 1h = Interrupt
5	RESERVED	R	0h	Reserved
4	INT_LTCH1[4]	R	0h	Interrupt due to Thermal Warning 135C 0h = No interrupt 1h = Interrupt
3	INT_LTCH1[3]	R	0h	Interrupt due to Thermal Warning 125C 0h = No interrupt 1h = Interrupt
2	INT_LTCH1[2]	R	0h	Interrupt due to Thermal Warning 115C 0h = No interrupt 1h = Interrupt
1	INT_LTCH1[1]	R	0h	Interrupt due to Thermal Warning 105C 0h = No interrupt 1h = Interrupt
0	RESERVED	R	0h	Reserved

7.1.45 INT_LATCH_2 Register (Address = 62h) [Reset = 00h]

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This register provides the status of latched interrupts.

Table 7-46 INT_LATCH_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH2[7]	R	0h	Interrupt due to watchdog expiry 0h = No interrupt 1h = Interrupt
6	RESERVED	R	0h	Reserved
5	INT_LTCH2[5]	R	0h	Interrupt due to frame out of sync 0h = No interrupt 1h = Interrupt
4	INT_LTCH2[4]	R	0h	Interrupt due to PLL clock error 0h = No interrupt 1h = Interrupt
3	INT_LTCH2[3]	R	0h	Interrupt due to tdm error 0h = No interrupt 1h = Interrupt
2	INT_LTCH2[2]	R	0h	Interrupt due to ratio change error flag 0h = No interrupt 1h = Interrupt
1	INT_LTCH2[1]	R	0h	Interrupt due to fs change error flag 0h = No interrupt 1h = Interrupt
0	INT_LTCH2[0]	R	0h	Interrupt due to invalid ratio fs flag 0h = No interrupt 1h = Interrupt

7.1.46 INT_LATCH_3 Register (Address = 63h) [Reset = 00h]

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This register provides the status of latched interrupts.

Table 7-47 INT_LATCH_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH3[7]	R	0h	Interrupt due to over temperature detected 0h = No interrupt 1h = Interrupt
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	INT_LTCH3[3]	R	0h	Interrupt due to Class-D Over current protection 0h = No interrupt 1h = Interrupt
2	INT_LTCH3[2]	R	0h	Interrupt due to Over voltage on PVDD supply. 0h = No interrupt 1h = Interrupt
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.47 INT_LATCH_4 Register (Address = 64h) [Reset = 00h]

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This register provides the status of latched interrupts.

Table 7-48 INT_LATCH_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH4[7]	R	0h	Interrupt due to VBAT under voltage detection 0h = No interrupt 1h = Interrupt
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	INT_LTCH4[2]	R	0h	Interrupt due to clock halt flag 0h = No interrupt 1h = Interrupt
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.48 NG_IDLE_STATUS Register (Address = 65h) [Reset = 00h]

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This register provides the status of noise gate.

Table 7-49 NG_IDLE_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	NG_STATUS	R	0h	Noise mode status bit 0h = Device not in Noise gate mode 1h = Device in Noise gate mode
6	MUSIC_EFF_STATUS	R	0h	Music efficiency mode status bit 0h = Device not in music efficiency mode 1h = Device in music efficiency mode
5-0	RESERVED	R	0h	Reserved

7.1.49 REV_ID Register (Address = 78h) [Reset = 00h]

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Returns Revision ID (REV_ID).

Table 7-50 REV_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	REV_ID[3:0]	R	0h	Returns the revision ID.
3-0	RESERVED	R	0h	Reserved

7.1.50 BOOK Register (Address = 7Fh) [Reset = 00h]

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Device's memory map is divided into pages and books. This register sets the book.

Table 7-51 BOOK Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	BOOK[7:0]	R/W	0h	Sets the device book. 0h = Book 0 1h = Book 1 FFh = Book 255