SLASFC6A August   2024  – August 2025 TAS2120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1  PurePath™ Console 3 Software
      2. 6.4.2  Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3  Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4  Internal Boost
      5. 6.4.5  Boost Share
      6. 6.4.6  External Class-H Boost Controller
      7. 6.4.7  Supply Voltage Monitors
      8. 6.4.8  Thermal Protection
      9. 6.4.9  Clocks and PLL
        1. 6.4.9.1 Auto clock based wakeup and clock errors
      10. 6.4.10 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1  PAGE 0 Registers
    2. 7.2  PAGE 1 Registers
    3. 7.3  PAGE 2 Registers
    4. 7.4  PAGE 3 Registers
    5. 7.5  PAGE 4 Registers
    6. 7.6  PAGE 5 Registers
    7. 7.7  PAGE 6 Registers
    8. 7.8  PAGE 7 Registers
    9. 7.9  PAGE 8 Registers
    10. 7.10 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2 Typical Application

Diagrams below show typical application connections for Internal Boost and for External PVDD mode. SEL1_I2C pin is used for HW Mode selection or I2C Mode selection of the Device.

System can use same 1.8V supply source to power the IOVDD and VDD if required. The decoupling caps C2 and C3 should be placed close to the device pins.

VBAT, VDD, PVDD power rails are critical for device performance and wide trace should be used from the source PMIC to these pins to minimize parasitic inductance. Supply ripple should be kept at minimum for these rails and should be connected to common supply planes.

Errata: Additional 2mA to 3mA current consumption expected if IRQZ singal is pulled high. Read more details in What to Do and What Not to Do section.

TAS2120 Application Diagram for 1S Battery system Figure 8-1 Application Diagram for 1S Battery system

TAS2120 Application Diagram for 2S Battery system Figure 8-2 Application Diagram for 2S Battery system
TAS2120 Application Diagram for External PVDD system Figure 8-3 Application Diagram for External PVDD system
TAS2120 Application Diagram for Boost Share Topology Figure 8-4 Application Diagram for Boost Share Topology
Table 8-1 Recommended External Components
Component Description Specification Min Typ Max Unit
L1 Boost Convertor Inductor Inductance, 20% Tolerance 0.47 1 µH
Saturation current 5.3 A
L2, L3 Optional EMI Filter Inductors (must use C10, C11 if L2, L3 are used) DC Current 2 A
C1, C2 DREG, IOVDD decap Capacitance, 20% tolerance 1 µF
Voltage rating 2 6.3 V
C3 VDD decap Capacitance, 20% tolerance 2.2 µF
Voltage rating 2 6.3 V
C4 VBAT decap Capacitance, 20% tolerance 1 µF
Voltage rating 6.3 10 V
C5 1S Battery Power decap Capacitance, 20% tolerance 10 µF
Voltage rating 6.3 10 V
C6 PVDD Low ESL decap Capacitance, 20% tolerance 0.1 µF
Voltage rating 16 25 V
C7, C8, C12 PVDD Power decap Capacitance, 20% tolerance 10 µF
Voltage rating 16 25 V
Effective total PVDD Capacitance after deratings for 1S battery systems 3 µF
C9 GREG decap Capacitance, 20% tolerance 0.1 µF
Voltage rating 6.3 10 V
C10, C11 Optional EMI Filter capacitors (must use L2, L3 if C10, C11 are used) Voltage rating 2xPVDD V