SLASFC6A August   2024  – August 2025 TAS2120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1  PurePath™ Console 3 Software
      2. 6.4.2  Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3  Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4  Internal Boost
      5. 6.4.5  Boost Share
      6. 6.4.6  External Class-H Boost Controller
      7. 6.4.7  Supply Voltage Monitors
      8. 6.4.8  Thermal Protection
      9. 6.4.9  Clocks and PLL
        1. 6.4.9.1 Auto clock based wakeup and clock errors
      10. 6.4.10 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1  PAGE 0 Registers
    2. 7.2  PAGE 1 Registers
    3. 7.3  PAGE 2 Registers
    4. 7.4  PAGE 3 Registers
    5. 7.5  PAGE 4 Registers
    6. 7.6  PAGE 5 Registers
    7. 7.7  PAGE 6 Registers
    8. 7.8  PAGE 7 Registers
    9. 7.9  PAGE 8 Registers
    10. 7.10 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.1 Layout Guidelines

  • Use wide traces for signals that carry high current and avoid VIAs wherever possible. If VIAs can't be avoided, multiple VIAs should be added to enable low parasitic inductance and high current capability. These include traces for PVDD, VBAT, VDD, PGND, BGND, GND, OUT_P and OUT_N.
  • PGND and BGND signal should be directly connected and shorted to the ground plane of board to minimize parasitic inductance. Common inductance between ground pins (eg GND and PGND or GND and BGND common routing) before connecting to ground plane should be avoided.
  • The coupling between high switching signal traces like OUT_P, OUT_N, SW, should be avoided from sensitive low voltage signals.
  • Minimize capacitance between high switching lines like OUT_P, OUT_N, SW, to ground/static nodes. Larger capacitance will result in efficiency drop. Coupling between OUT_P and OUT_N will also cause degraded efficiency.
  • VBAT routing to the boost inductor and the device VBAT pin should be star connected to the common VBAT supply plane. Ensure the decoupling capacitor C4 is placed close to the device and decoupling capacitor C5 is placed close to the inductor.
  • Place the boost inductor between VBAT and SW close to the device terminal with no VIAs between device terminal and the inductor. VBAT routing to the boost inductor should be routed with minimal routing resistance to achieve best performance from device.
  • Decoupling capacitors should be placed close to the device. Smallest possible package size is recommended for the decaps to achieve best performance from device. DREG, VDD, IOVDD, VBAT (C4 cap), PVDD low ESL (C6 cap) are recommended to be 0201 case size or lower. VIAs between decapacitors and device pins should be avoided, or multiple VIAs added to minimize parasitic inductances.
  • All decoupling capacitor's ground terminal should be strongly connected to the ground plane with multiple ground VIAs. The ground routing loop between the cap ground and the device ground pins should be minimized.
  • For VDD Y-bridge functionality, the routing from the host PMIC to the device VDD should be wide supply plane trace with minimal routing parasitic inductance.
  • For the capacitor between GREG-PVDD (C9 cap), PVDD side of capacitor should not be connected directly to the PVDD decoupling capacitors (C6, C7 and C8), and should be connected as close as possible to the device PVDD pin.
  • In external PVDD mode of operation, SW pin should be left floating and not connected to any supply or ground signals.