SLASFC6A August   2024  – August 2025 TAS2120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1  PurePath™ Console 3 Software
      2. 6.4.2  Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3  Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4  Internal Boost
      5. 6.4.5  Boost Share
      6. 6.4.6  External Class-H Boost Controller
      7. 6.4.7  Supply Voltage Monitors
      8. 6.4.8  Thermal Protection
      9. 6.4.9  Clocks and PLL
        1. 6.4.9.1 Auto clock based wakeup and clock errors
      10. 6.4.10 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1  PAGE 0 Registers
    2. 7.2  PAGE 1 Registers
    3. 7.3  PAGE 2 Registers
    4. 7.4  PAGE 3 Registers
    5. 7.5  PAGE 4 Registers
    6. 7.6  PAGE 5 Registers
    7. 7.7  PAGE 6 Registers
    8. 7.8  PAGE 7 Registers
    9. 7.9  PAGE 8 Registers
    10. 7.10 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.4 Internal Boost

The TAS2120 internal processing algorithm automatically enables the boost when needed. A look-ahead algorithm monitors the battery voltage and the digital audio stream. When the speaker output approaches the battery voltage the boost is enabled in-time to supply the required speaker output voltage. When the boost is no longer required it is disabled and bypassed to maximize efficiency. The boost can be configured in one of two modes. The first is low in-rush (Class-G) supporting only boost on-off and has the lowest in-rush current. The second is high-efficiency (Class-H) where the boost voltage level is adjusted to a value just above what is needed. This mode is more efficient but has a higher in-rush current to quickly transition the levels. This can be configured using BST_MODE[1:0] register bits.

TAS2120 Boost Mode Signal Tracking ExampleFigure 6-10 Boost Mode Signal Tracking Example
Table 6-31 Boost Mode
BST_MODE[1:0]BOOST MODE
00Class-H - High efficiency (default)
01Class-G - Low in-rush
10Always On
11Always Off - Pass-through

The boost can be enabled and disabled using BST_EN register. When driving the Class-D amplifier using an external supply through the PVDD pin, the boost should be disabled and the SW pin should be left floating.

Table 6-32 Boost Enable
BST_ENBOOST IS
0Disabled (External PVDD mode)
1Enabled (default)

The maximum boost voltage is set by VBOOST_MAX_CTRL[7:0]. When operating in class-G mode, the boost when needed will be at this voltage. In class-H mode of operation the boost voltage is automatically selected based on the audio signal but will not exceed this set value. In class-H mode, the class-H controller controls the Boost with a minimum step size of 33mV to generate the required PVDD voltage. The max boost voltage that the device generates is controlled by VBOOST_MAX_CTRL[7:0] and it can be configured with a step size of 66mV.

Table 6-33 Boost Max Regulation Voltage
VBOOST_MAX_CTRL[7:0] BOOST VOLTAGE (V)
0x00 - 0x53 Reserved
0x54 5.54 V
0x55 5.61 V
... …..steps of 66mV per LSB step …...
0xA7 11.02 V
... …..steps of 66mV per LSB step …...
0xE3 14.98 V (default)
0xE4 15.05 V
0xE5 15.11V
0xE6 - 0xFF Reserved
At light loads (eg. near zero cross of sine waves), the boost automatically enters PFM mode to improve the system efficiency. When the Boost is running in PFM mode, the minimum pulse frequency can be adjusted using BST_MIN_FREQ_SEL. Setting a higher PFM frequency will ensure the Boost frequency is always above the set threshold at the cost of increasing the system power consumption.
Table 6-34 Active Mode PFM Lower Frequency Limit
BST_MIN_FREQ_SEL[1:0] LOWER LIMIT
00 No lower limit (default)
01 25 kHz
10 50 kHz
11 RESERVED

The peak current drawn by the boost is controlled using BST_ILIM[23:0] register and it limits the current drawn from the VBAT supply. This setting allows flexibility in the inductor selection for various saturation currents. The system should always use inductors which have minimum saturation current (ISAT) atleast 5% higher than programmed BST_ILIM setting. The Boost circuit can go unstable if the inductor's ISAT is lower than the BST_ILIM setting. The current limit can be adjusted in 39.1 mA steps with a range from 1.5A to 5.1A using PPC3 Software.

The change in boost configurations like BST_ILIM, VBOOST_MAX_CTRL etc requires re-tuning of device parameters such as CLASSH_TUNING_xx[23:0] registers to achieve best performance while ensuring no functionality failures. This configuration should be changed using PPC3 tool to enable automatic reconfiguration of all the associated device parameters.

For multiple channel systems, the boost phase can be shifted to ensure each device will draw peak current from the battery at different instance of times and enable lower instantaneous peak current from the battery. The boost syncing among multiple devices is enabled using BOOST_PHASE_SYNC_EN. The individual device boost phase can be automatically configured to different values using the I2C target address device detected by using BOOST_PHASE_FROM_ADDRESS_PIN register, or it can be manually configured using BOOST_PHASE register. The Boost phase shift is done by each device using the FSYNC pulse to synchronize each device and all the devices which require the Boost phase synchronization should be connected to same FSYNC from the host in the system.

Table 6-35 Boost Sync
BOOST_PHASE_SYNC_EN Status
0 Disabled
1 Enabled(default)
Table 6-36 Boost Phase selection from I2C target address
BOOST_PHASE_FROM_ADDRESS_PIN Status
0 Disabled(default)
1 Enabled
Table 6-37 Boost Phase manual selection (when BOOST_PHASE_FROM_ADDRESS_PIN = 0)
BOOST_PHASE[1:0] Phase Delay
00 Phase shift is 0ns (default)
01 Phase shift is 65ns (~90° for max clock)
10 Phase shift is 130ns (~180° for max clock)
11 Phase shift is 195ns (~270° for max clock)