SLVSDF3F MARCH 2017 – JANUARY 2019 TPSM846C23
For proper operation, the minimum required input capacitance network consists of four 22-µF (or two 47-µF) ceramic capacitors plus a 330-µF bulk capacitor. See capacitors C1 thru C5 in Figure 13. Place the ceramic capacitors as close as possible to the VIN pins. Connect the ground return path of the capacitors to PGND pins 42, 43, 54, and 59 of the TPSM846C23.
The minimum required output capacitance network consists of four 47-µF (or two 100µF) ceramic capacitors plus two 470-µF, low-ESR polymer capacitors. See capacitors C10 thru C15 in Figure 13. The combined ESR of the polymer capacitors must not be greater than 5 mΩ. Place the ceramic capacitors as close as possible to the VOUT and PGND pins of the module. This minimum network insures good transient response and minimal ripple amplitude. The total amount of output capacitance determines the values of the frequency compensation network. For more details see Setting the Compensation Network.
Additionally, the analog power path (VINBP) requires its own bypass network consisting of a 10-nF ceramic capacitor (C8 in Figure 13) and 1-µF ceramic capacitor (C7 in Figure 13) connected directly across pins 50 and 51 of the module. For proper operation, the two internal power supply rails of the module must also be bypassed. The 6.5-V rail (BP6) requires a 4.7-µF ceramic capacitor (C6 in Figure 13) placed across pins 48 and 49 of the module with short, direct traces. The 3.3-V rail (BP3) requires a 2.2-µF ceramic capacitor (C9 in Figure 13) placed very close to pins 47 and 51.