SLVSDF3F MARCH 2017 – JANUARY 2019 TPSM846C23
Timing and electrical characteristics of the PMBus interface specification can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.3 available at http://pmbus.org. The TPSM846C23 device supports both the 100-kHz and 400-kHz bus timing requirements. The devices do not stretch pulses when communicating with the master device.
Communication over the PMBus interface can support the packet error checking (PEC) scheme if desired. If the master supplies clock (CLK pin) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used.
The devices support a subset of the commands in the PMBus 1.3 Power Management Protocol Specification. See Supported PMBus Commands for more information
The devices contain nonvolatile memory that stores configuration settings and scale factors. However, the device does not automatically save the settings programmed into this nonvolatile memory. The STORE_DEFAULT_ALL (11h) or STORE_USER_ALL (15h) command must be used to commit the current settings to nonvolatile memory as device defaults. The settings that are capable of being stored in nonvolatile memory are noted in the detailed command descriptions.