SLVSDF3F MARCH 2017 – JANUARY 2019 TPSM846C23
When two TPSM846C23 devices are paralleled, the SYNC pins of the master and the slave must be supplied with a 50% duty-cycle clock signal at the desired switching frequency. The master device locks to the rising edge of the clock; the slave locks to the falling edge. The 50% duty cycle requirement insures the modules operate 180° out of phase to minimize ripple. Both the master and slave module must have an RRT resistor present whose value sets a switching frequency within ±20% of the SYNC clock frequency. See Parallel Application for more information when paralleling devices.