SLVSDF3F MARCH 2017 – JANUARY 2019 TPSM846C23
This bit sets the output voltage overvoltage response to either ignore or not. The default for this bit is 1.
|0||The PMBus device continues operation without interruption. Note: In this ignore fault response mode, the associated fault status bits is set. Additionally, SMBALERT remains triggered if it is not masked.|
|1||The PMBus device shuts down and restarts according to RS[2:0].|