SLVSDF3F MARCH 2017 – JANUARY 2019 TPSM846C23
To operate two TPSM846C23 devices in parallel, one of the devices must act as the master and the other act as a slave. To configure one of the devices as the slave device, connect a 1-kΩ resistor between the device FB pin and BP3 pin. Additionally, the SYNC, VSHARE, and ISHARE pins of both devices must be connected as shown in Figure 18. Both devices share the same VSHARE voltage. Essentially, the internal COMP voltage is shared between the two devices by connecting the VSHARE pin of each device together. By connecting the ISHARE pin of each device, the sensed current in each phase is compared, then the error current is added into the internal COMP. The resulting voltage is compared with the PWM ramp to generate the PWM pulse. This current sharing loop maintains the current balance between devices.
In addition to sharing the same internal COMP voltage, the VSHARE pin is also used for fault communication between the loop master and slave devices. The VSHARE pin voltage is pulled low if any device encounters any fault conditions so that the other device sharing VSHARE pin is alerted and stops switching accordingly.
The master and slave devices must be set to two different PMBus addresses. The telemetry data from the master and slave devices must be retrieved seperately.
When configured for parallel operation, the SYNC pins of the master and the slave must be supplied with a 50% duty cycle clock signal at the desired switching frequency. The master device locks to the rising edge of the clock; the slave locks to the falling edge. The 50% duty cycle requirement insures the modules operate 180° out of phase to minimize ripple. Both the master and slave module must have an RRT resistor present whose value sets a switching frequency within ±20% of the SYNC clock frequency.
An optional high-frequency capacitor can be added between the VSHARE pin and ground in noisy systems, but the capacitance must not exceed 10 pF.
If operating conditions result in an on-time pulse width of ≤ 150 ns, jitter may be observed on the master and slave PH pins. The addition of a 10-kΩ resistor in series with the ISHARE connection between the devices helps to reduce, but may not eliminate the jitter.
To evaluate the TPSM846C23 in parallel configuration, an evaluation board is available. Also refer to the Operating TPSM846C23 in Parallel user's guide for operation instructions and layout recommendations.