SNAA377 December 2025 LMK05318 , LMK05318B , LMK5B12204 , LMK5B12212 , LMK5B33216 , LMK5B33414 , LMK5C22212A , LMK5C23208A , LMK5C33216 , LMK5C33216A , LMK5C33414A
Table 1-1 lists the definition for each abbreviation and/or key terminology used in the document.
| TERM | DEFINITION |
|---|---|
| LVPECL | Low Voltage Positive Emitter Coupled Logic |
| LVDS | Low Voltage Differential Signaling |
| HCSL | High Speed Current Steering Logic |
| LP-HCSL | Low Power High Speed Current Steering Logic |
| LVCMOS | Low Voltage Complementary Metal Oxide Semiconductor |
| P and N | Complimentary pair of a differential signal. P is the non-inverted signal and N is the inverted signal. |
| Single-ended | One input or output signal (such as LVCMOS) |
| Differential | A pair of "P" and "N" input or output signals (such as LVPECL) |
| PCB | Printed circuit board |
| ZO | Transmission line impedance, characteristic impedance, PCB trace impedance(1) |
| VCM | Common-mode voltage, where VCM = (P + N) /2, the average of the P and N signal |
| VIH | Input high voltage level |
| VIL | Input low voltage level |
| VOH | Ouput high voltage level |
| VOL | Output low voltage level |
| VID | Single-ended input voltage swing level (amplitude), where VID = VIH − VIL |
| VOD | Single-ended output voltage swing level (amplitude), where VOD = VOH −VOL |
| VPP | Differential peak-to-peak voltage, where VPP = 2 × VID or 2 × VOD |
| VDD or VCC | Supply voltage |
| IBIS | Input/Output Buffer Information Specification |