SNAA421 November   2025 LMK05318B , LMK5B12204 , LMK5B33216 , LMK5B33414 , LMK5C33216A , LMK5C33414A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Start Here: Using TICS Pro for Configuration and Readback
    1. 1.1 TICS Pro Status Page
    2. 1.2 TICS Pro Default Setting
  5. 2Debug Procedure: From Device Start-Up to Locked Output State
    1. 2.1 Is the APLL Reference Valid?
      1. 2.1.1 Check Status of APLL Reference
      2. 2.1.2 Debug APLL Reference
    2. 2.2 Is the APLL Locked?
      1. 2.2.1 Check Status of APLL Lock
      2. 2.2.2 Debug APLL Lock
    3. 2.3 Is the DPLL Reference Valid?
      1. 2.3.1 Check Status of DPLL Reference Validation
      2. 2.3.2 Debug DPLL Reference Validation
    4. 2.4 Is the DPLL Selecting a Reference?
      1. 2.4.1 Check Status of DPLL Reference Selection
      2. 2.4.2 Debug DPLL Reference Selection
    5. 2.5 Is the DPLL Frequency Locked?
      1. 2.5.1 Check Status of DPLL Frequency Lock
      2. 2.5.2 Debug DPLL Frequency Lock
    6. 2.6 Is the DPLL Phase Locked?
      1. 2.6.1 Check Status of DPLL Phase Lock
      2. 2.6.2 Debug DPLL Phase Lock
  6. 3Summary
  7. 4References

2.2 Is the APLL Locked?

At this stage in the debug, the XO input (or cascaded source) must be considered valid. The APLL automatically attempts to lock to the APLL reference after a power-on reset (POR), hardware reset, or software reset. The APLL reference provides the phase and frequency reference for the phase frequency detector (PFD). The PFD compares the APLL reference against the APLL VCO feedback clock to get a phase error. The charge pump converts the phase error into a correction current. The APLL loop filter then converts the correction current to a correction voltage, which tunes the VCO output frequency and keeps the VCO output synchronized to the APLL reference. The APLL reference, PFD, charge pump, APLL loop filter, and VCO are key contributors to getting a locked APLL.

Additionally, the path to DPLL lock must be considered and can be simplified into the four sequential states (listed below) with each state impacting the APLL output behavior. Refer to the LMK data sheet for more details on the DPLL lock states.

  1. Holdover: Free-Run

    After APLL initialization, the free-run state is entered and the initial frequency accuracy of the APLL outputs is determined by the free-run tuning word register. The APLL reference determines the frequency accuracy and stability of the APLL outputs. If the free-run tuning word is not 0, then there is a frequency offset applied to the APLL output.

  2. DPLL Lock Acquisition

    The DPLL continuously steers and updates the APLL numerator to achieve DPLL frequency and phase lock. The APLL output clocks transition from locking to the APLL reference to locking to the DPLL reference.

  3. DPLL Lock

    During the DPLL lock state, the DPLL reference determines the frequency accuracy and stability of the APLL outputs, predominately below the DPLL loop bandwidth (LBW). DCO adjustments can impact the accuracy and stability depending on the DCO adjustment value and rate. In the DPLL lock state, the LMK device averages the DPLL reference frequency to accumulate history data (if the tuning word history is enabled).

  4. Holdover: History, Free-Run, Last Control Word

    The holdover state is entered when the DPLL reference becomes invalid. Upon entering holdover, the frequency accuracy of the APLL outputs are determined by the tuning word history (averaged DPLL input frequency), the DPLL free-run register, or the last numerator word. The LMK device can successfully enter holdover with history if enough data is accumulated from the digital-loop filter (DLF) output during the programmed history averaging time. After an extended period of holdover, the frequency accuracy of the APLL outputs are determined by the APLL reference. During holdover, the stability of the APL output clocks changes because the DPLL reference no longer impacts below the DPLL LBW. Instead, the APLL reference alone determines the performance below the DPLL LBW.

If the APLL is locked but the DPLL is unlocked, proceed to Is the DPLL Reference Valid?. Otherwise, refer to Check Status of APLL Lock and Debug APLL Lock.