SNAA421 November 2025 LMK05318B , LMK5B12204 , LMK5B33216 , LMK5B33414 , LMK5C33216A , LMK5C33414A
Network synchronizers use a combination of a digital and analog phase-locked loops (DPLL and APLL) to provide input-to-output synchronization, output clock generation, and jitter cleaning capabilities. With the DPLL, the network synchronizer can support additional features such as hitless switching, holdover, digitally-controlled oscillators (DCO), and jitter cleaning for close-in phase noise (less than 1kHz offsets). The addition of a DPLL adds complexity and can result in more debug steps than a simple clock generator.
The purpose of the application note is to provide a step-by-step guide on how to debug network synchronizers, specifically on how to achieve DPLL phase lock, which is a common debug inquiry. The devices applicable to the application note are listed in Table 1-1. When referring to all of the devices listed, the application note uses the term LMK device for a generalized name. When referring to a particular device grouping, the application note uses the family name.
| DEVICE FAMILY NAME | DEVICE PART NUMBERS IN FAMILY |
|---|---|
| LMK05318(1) | LMK05318 |
| LMK05318B | LMK05318B, LMK05318B-Q1, LMK5B12204 |
| LMK5C(1) | LMK5C33216 |
| LMK5B | LMK5B33216, LMK5B33414, LMK5B12212 |
| LMK5CA | LMK5C33216A, LMK5C33414A, LMK5C33216AS1, LMK5C33414AS1, LMK5C22212A, LMK5C23208A |