SNAA421 November   2025 LMK05318B , LMK5B12204 , LMK5B33216 , LMK5B33414 , LMK5C33216A , LMK5C33414A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Start Here: Using TICS Pro for Configuration and Readback
    1. 1.1 TICS Pro Status Page
    2. 1.2 TICS Pro Default Setting
  5. 2Debug Procedure: From Device Start-Up to Locked Output State
    1. 2.1 Is the APLL Reference Valid?
      1. 2.1.1 Check Status of APLL Reference
      2. 2.1.2 Debug APLL Reference
    2. 2.2 Is the APLL Locked?
      1. 2.2.1 Check Status of APLL Lock
      2. 2.2.2 Debug APLL Lock
    3. 2.3 Is the DPLL Reference Valid?
      1. 2.3.1 Check Status of DPLL Reference Validation
      2. 2.3.2 Debug DPLL Reference Validation
    4. 2.4 Is the DPLL Selecting a Reference?
      1. 2.4.1 Check Status of DPLL Reference Selection
      2. 2.4.2 Debug DPLL Reference Selection
    5. 2.5 Is the DPLL Frequency Locked?
      1. 2.5.1 Check Status of DPLL Frequency Lock
      2. 2.5.2 Debug DPLL Frequency Lock
    6. 2.6 Is the DPLL Phase Locked?
      1. 2.6.1 Check Status of DPLL Phase Lock
      2. 2.6.2 Debug DPLL Phase Lock
  6. 3Summary
  7. 4References

2.2.2 Debug APLL Lock

If the status is undesired, run through the following debug steps.

  1. Disable the DPLL to confirm APLL lock.

    Confirm the APLL is configured properly and can achieve lock by disabling the DPLL. If the DPLL is enabled, the DPLL can rail the APLL which can cause the frequency to unlock and make the debug more complicated. Re-enable the DPLL once APLL lock is validated.

  2. Recalibrate the APLL by issuing a software reset.

    Each APLL VCO must be calibrated to achieve APLL lock and deliver the best phase noise performance. The VCO calibration establishes the best operating point within the VCO tuning range. After POR, hardware reset, or software reset, the VCO calibration is executed automatically. The APLL reference must be stable and considered valid before the start of calibration to provide a successful calibration and APLL lock. The output drivers are held in a muted state until the VCO calibration completes and the APLL locks. If you are not getting an APLL lock, try issuing a software reset after loading the register configuration. The best practice is to recalibrate the VCO whenever the PFD, charge pump, APLL loop filter, or APLL N divider registers are modified.

  3. Check the PFD inputs by probing the GPIO pins.

    The PFD has two inputs: the APLL R divider path (from the XO input) and the APLL N divider path (from the VCO), as shown in Figure 2-2. The GPIO pins of the LMK devices can be configured as "APLL R divided by 2" and "APLL N divided by 2" signals which applies a divide by 2 to each path to reduce the GPIO output frequency. Configure the two GPIO pins per Table 2-12 and Table 2-27. Note that the APLL R divider is unavailable when R=1 (bypassed); in this case, probe the external APLL reference. Probe the two signals using an oscilliscope. Confirm that the two signals are present, have the same frequency, and are frequency-locked to each other. During a locked APLL state, the two signals are triggered to each other with no drifting observed on the oscilliscope.

    APLL R and APLL N Divider PathsFigure 2-2 APLL R and APLL N Divider Paths
    Table 2-7 APLL R Divided by 2 - Register Setting
    DEVICE FAMILYTICS PRO FIELD NAMEPIN NAMEAPLL R DIVIDED BY 2
    REGISTER SETTING
    BAW APLLAPLL2APLL1(2)
    LMK05318B, LMK05318PLLx R Divider,
    div-by-2    		STATUS0N/A(1)R48[6:0] = 0x0FN/A
    STATUS1N/A(1)R49[6:0] = 0x0FN/A
    LMK5B or LMK5CAPLLx R-Divider Divided By 2Required for any GPIOxR70[0] = 1
    R872[3] = 1    		R70[0] = 1
    R808[3] = 1    		R70[0] = 1
    R736[3] = 1
    GPIO0R57[6:0] = 0x55R57[6:0] = 0x54R57[6:0] = 0x53
    GPIO1R58[6:0] = 0x55R58[6:0] = 0x54R58[6:0] = 0x53
    GPIO2R59[6:0] = 0x55R59[6:0] = 0x54R59[6:0] = 0x53
    (1) APLL R divider signal is not available. Probe the external APLL reference instead and trigger the oscilliscope on APLL N-divider path (the lower frequency).
    (2) Column is not applicable for LMK5B12212 or LMK5C22212A.
    Table 2-8 APLL N Divided by 2 - Register Setting
    DEVICE FAMILYTICS PRO FIELD NAMEPIN NAMEAPLL N DIVIDED BY 2
    REGISTER SETTING
    BAW APLLAPLL2APLL1(1)
    LMK05318B, LMK05318PLLx N Divider,
    div-by-2    		STATUS0R48[6:0] = 0x05R48[6:0] = 0x08N/A
    STATUS1R48[6:0] = 0x05R49[6:0] = 0x08N/A
    LMK5B or LMK5CAPLLx N-Divider,
    Divided By 2    		Required for any GPIOxR70[0] = 1
    R872[3] = 1    		R70[0] = 1
    R808[3] = 1    		R70[0] = 1
    R736[3] = 1
    GPIO0R57[6:0] = 0x52R57[6:0] = 0x51R57[6:0] = 0x50
    GPIO1R58[6:0] = 0x52R58[6:0] = 0x51R58[6:0] = 0x50
    GPIO2R59[6:0] = 0x52R59[6:0] = 0x51R59[6:0] = 0x50
    (1) Column is not applicable for LMK5B12212 or LMK5C22212A.
  4. Check the APLL charge pump settings.

    Try using the charge pump register settings provided by the Default Configuration tab in TICS Pro Software. Too much charge pump current can oversaturate the APLL resulting in unstable APLL outputs. Too little charge pump current can cause the APLL to unlock and become an open-loop.

  5. Check the loop filter settings.

    Try using the loop filter register settings provided by the Default Configuration tab in TICS Pro Software. Additionally, confirm the external capacitor applied to the LFx pin is per data sheet recommendation. The external capacitor is the "C2" for the respective APLLx loop filter.

  6. Check the APLL tuning voltage by probing the LFx pin.

    Measure the voltage of the LFx pin over time to observe the trend. During normal operation, the voltage varies over time due to variation in the APLL reference frequency (when the APLL is locked), DPLL reference frequency (when the DPLL is locked), and temperature. The typical tuning voltage is somewhere in the middle. Too low or too high can mean the APLL has railed to an incorrect frequency. If the DPLL is enabled, the tuning voltage can be railed (< 0.1V or > 2.4V) because the DPLL drives the APLL to rail off. A reading of 0V is not expected behavior and can be due to a damaged or improperly soldered device. If the voltage is not changing, but is not 0V, contact TI by posting on the public TI E2E forum for further assistance.