SNAA421 November   2025 LMK05318B , LMK5B12204 , LMK5B33216 , LMK5B33414 , LMK5C33216A , LMK5C33414A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Start Here: Using TICS Pro for Configuration and Readback
    1. 1.1 TICS Pro Status Page
    2. 1.2 TICS Pro Default Setting
  5. 2Debug Procedure: From Device Start-Up to Locked Output State
    1. 2.1 Is the APLL Reference Valid?
      1. 2.1.1 Check Status of APLL Reference
      2. 2.1.2 Debug APLL Reference
    2. 2.2 Is the APLL Locked?
      1. 2.2.1 Check Status of APLL Lock
      2. 2.2.2 Debug APLL Lock
    3. 2.3 Is the DPLL Reference Valid?
      1. 2.3.1 Check Status of DPLL Reference Validation
      2. 2.3.2 Debug DPLL Reference Validation
    4. 2.4 Is the DPLL Selecting a Reference?
      1. 2.4.1 Check Status of DPLL Reference Selection
      2. 2.4.2 Debug DPLL Reference Selection
    5. 2.5 Is the DPLL Frequency Locked?
      1. 2.5.1 Check Status of DPLL Frequency Lock
      2. 2.5.2 Debug DPLL Frequency Lock
    6. 2.6 Is the DPLL Phase Locked?
      1. 2.6.1 Check Status of DPLL Phase Lock
      2. 2.6.2 Debug DPLL Phase Lock
  6. 3Summary
  7. 4References

2.5 Is the DPLL Frequency Locked?

At this stage in the debug, the APLL and the DPLL references are valid input signals and the APLL is locked. The next step is to check the frequency lock state of the DPLL. If the DPLL registers are misconfigured, then the DPLL can rail the APLL causing the output clocks to be off in frequency (with a frequency offset applied that is within the VCO frequency pulling range). When the DPLL is frequency locked, the VCO output and output clocks are frequency locked to the selected DPLL input. The locked output clocks slew at a rate defined by the DLF until the desired output frequency is reached (near 0ppm error).

The DPLL frequency lock state can be identified by checking the respective status bit or debugging the time-to-digital converter (TDC). The TDC compares the phase error between the DPLL reference clock after the R divider (DPLL R path) and the respective VCO output clock after the feedback divider (DPLL FB path). The TDC phase error is generated as a digital correction word and is filtered by the DLF. The DLF output adjusts the APLL N divider numerator to pull the VCO frequency into lock with the DPLL reference. Figure 2-3 shows the block diagram view of the DPLL R and DPLL FB paths to the TDC.

DPLL R and DPLL FB Paths Figure 2-3 DPLL R and DPLL FB Paths

If the DPLL is frequency locked but not phase locked to the DPLL input, proceed to Is the DPLL Phase Locked?. Otherwise, refer to Check Status of DPLL Frequency Lock and Debug DPLL Frequency Lock.