SNAA421 November   2025 LMK05318B , LMK5B12204 , LMK5B33216 , LMK5B33414 , LMK5C33216A , LMK5C33414A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Start Here: Using TICS Pro for Configuration and Readback
    1. 1.1 TICS Pro Status Page
    2. 1.2 TICS Pro Default Setting
  5. 2Debug Procedure: From Device Start-Up to Locked Output State
    1. 2.1 Is the APLL Reference Valid?
      1. 2.1.1 Check Status of APLL Reference
      2. 2.1.2 Debug APLL Reference
    2. 2.2 Is the APLL Locked?
      1. 2.2.1 Check Status of APLL Lock
      2. 2.2.2 Debug APLL Lock
    3. 2.3 Is the DPLL Reference Valid?
      1. 2.3.1 Check Status of DPLL Reference Validation
      2. 2.3.2 Debug DPLL Reference Validation
    4. 2.4 Is the DPLL Selecting a Reference?
      1. 2.4.1 Check Status of DPLL Reference Selection
      2. 2.4.2 Debug DPLL Reference Selection
    5. 2.5 Is the DPLL Frequency Locked?
      1. 2.5.1 Check Status of DPLL Frequency Lock
      2. 2.5.2 Debug DPLL Frequency Lock
    6. 2.6 Is the DPLL Phase Locked?
      1. 2.6.1 Check Status of DPLL Phase Lock
      2. 2.6.2 Debug DPLL Phase Lock
  6. 3Summary
  7. 4References

2.5.1 Check Status of DPLL Frequency Lock

The LMK device has a DPLL frequency lock detector that provides the lock state through the "loss of DPLL frequency lock" or "LOFL" bit. The DPLL LOFL bit definition is described in Table 2-22 and the status register is listed in Table 2-23. The registers to configure DPLL frequency lock detector are specified in Table 2-26.

Table 2-15 Loss of DPLL Frequency Lock - Status Bit Definition
BIT STATE MEANING DESCRIPTION
0 Desired result The DPLL reports frequency lock if the frequency error between the VCO output and the DPLL input is within the LOFL lock threshold.
1 Undesired result The DPLL reports unlocked while the frequency error exceeds the LOFL lock threshold and becomes unlocked when the frequency error exceeds the LOPL unlock threshold.
Table 2-16 Loss of DPLL Frequency Lock - Status Register
DEVICE FAMILY TICS PRO FIELD NAME LOSS OF DPLL FREQUENCY LOCK
REGISTER
BAW DPLL DPLL2 DPLL1
LMK05318B, LMK05318 LOFL_DPLL R80[7] N/A N/A
LMK5B, LMK5CA, LMK5C LOFL_DPLLx R36[6] R35[6] R34[6](1)
(1) Column is not applicable for LMK5B12212 or LMK5C22212A.
Table 2-17 Loss of DPLL Frequency Lock - Enable Setting
DEVICE FAMILY LOFL ENABLE
REGISTER SETTING
BAW DPLL DPLL2 DPLL1
LMK05318B, LMK05318 R79[4] = 1 N/A N/A
LMK5B, LMK5CA, LMK5C R22[5] = 1,
R528[7] = 1,
R561[7] = 0(1)		 R22[3] = 1,
R378[7] = 1		 R22[1] = 1,
R228[7] = 1(2)
(1) When R561[7] = 1, the R36[6] register reports the status of the BAW APLL digital lock detect (DLD), which is the BAW APLL frequency lock detector. When R561[7] = 0, the R36[6] register reports the status of the BAW DPLL DLD, which is the BAW DPLL loss of frequency lock detector. The APLL DLD is independent from the DPLL DLD.
(2) Column is applicable for LMK5B12212 or LMK5C22212A.
Table 2-18 Loss of DPLL Frequency Lock - Threshold Registers
DEVICE FAMILY LOFL - LOCK THRESHOLD
REGISTER(1)		 LOFL - UNLOCK THRESHOLD
REGISTER(1)
BAW DPLL DPLL2 DPLL1 BAW DPLL DPLL2 DPLL1
LMK05318B, LMK05318 R80[6:0] to R81,
R82 to R85,
R86 to R89		 N/A N/A R90 to R91,
R92 to R95,
R96 to R99		 N/A N/A
LMK5B, LMK5CA, LMK5C R536 to R539,
R540 to R543,
R528[6:0] to R529		 R386 to R389,
R390 to R393,
R378[6:0] to R379		 R236 to R239,
R240 to R243,
R228[6:0] to R229(2)		 R530[6:0] to R531 R380[6:0] to R381 R230[6:0] to R231(2)
(1) Use TICS Pro Software to configure the lock and unlock threshold register settings.
(2) Column is not applicable for LMK5B12212 or LMK5C22212A.