SPRUIY2A November   2024  – March 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating-Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
        1. 3.2.1.1 Required Instructions (RESET)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
        1. 3.2.2.1 Blocking and Masking (NMI)
        2. 3.2.2.2 Signal Propagation (NMI)
        3. 3.2.2.3 Stack (NMI)
        4. 3.2.2.4 Required Instructions (NMI)
      3. 3.2.3 RTINT (Real-Time Interrupt)
        1. 3.2.3.1 Blocking and Masking (RTINT)
        2. 3.2.3.2 Signal Propagation (RTINT)
        3. 3.2.3.3 Stack (RTINT)
        4. 3.2.3.4 Required Instructions (RTINT)
      4. 3.2.4 INT (Low-Priority Interrupt)
        1. 3.2.4.1 Blocking and Masking (INT)
        2. 3.2.4.2 Signal Propagation (INT)
        3. 3.2.4.3 Stack (INT)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Addressing Modes
    1. 4.1 Addressing Modes Overview
      1. 4.1.1 Documentation and Implementation
      2. 4.1.2 List of Addressing Mode Types
        1. 4.1.2.1 Additional Types of Addressing
      3. 4.1.3 Addressing Modes Summarized
    2. 4.2 Addressing Mode Fields
      1. 4.2.1 ADDR1 Field
      2. 4.2.2 ADDR2 Field
      3. 4.2.3 ADDR3 Field
      4. 4.2.4 DIRM Field
      5. 4.2.5 Additional Fields
    3. 4.3 Alignment and Pipeline Considerations
      1. 4.3.1 Alignment
      2. 4.3.2 Pipeline Considerations
    4. 4.4 Types of Addressing Modes
      1. 4.4.1 Direct Addressing
      2. 4.4.2 Pointer Addressing
        1. 4.4.2.1 Pointer Addressing with #Immediate Offset
        2. 4.4.2.2 Pointer Addressing with Pointer Offset
        3. 4.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 4.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 4.4.3 Stack Addressing
        1. 4.4.3.1 Allocating and De-allocating Stack Space
      4. 4.4.4 Circular Addressing Instruction
      5. 4.4.5 Bit Reversed Addressing Instruction
  7. 5Safety and Security Unit (SSU)
    1. 5.1 SSU Overview
    2. 5.2 Links and Task Isolation
    3. 5.3 Sharing Data Outside Task Isolation Boundary
    4. 5.4 Protected Call and Return
  8. 6Emulation
    1. 6.1 Overview of Emulation Features
    2. 6.2 Debug Terminology
    3. 6.3 Debug Interface
    4. 6.4 Execution Control Mode
    5. 6.5 Breakpoints, Watchpoints, and Counters
      1. 6.5.1 Software Breakpoint
      2. 6.5.2 Hardware Debugging Resources
        1. 6.5.2.1 Hardware Breakpoint
        2. 6.5.2.2 Hardware Watchpoint
        3. 6.5.2.3 Benchmark Counters
      3. 6.5.3 PC Trace
  9. 7Revision History

4.2.1 ADDR1 Field

This is a 16-bit field for indirect encoding of addresses that can be used in all "Pointer Addressing" and "Stack Addressing" modes.

Table 4-2 shows the various ways the 16 bits can be used to encode the address.

Table 4-2 ADDR1 Field Encodings
ADDR1 Field: (Ax = A0 to A14, Aj = A0 to A14, Ak = A0 to A3)
Mnemonic 2 Shorthand Address Generation 47 46 45 43 42 41 40 39 38 37 36 35 34 33 32 31
Mnemonic Shorthand Address Generation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
*(Ax+#u10imm) *Ax[#u10imm] addr = Ax + #u10imm (#u10imm = 0 to 1KB range) 0 0 #u10imm Ax[0-14] 1
*(Ax+#u10imm<<2) *Ax[#u10imm] addr = Ax + #u10imm<<2 (#u10imm << 2 = 0 to 4KB range, 4B steps) 0 1 #u10imm Ax[0-14] 1
*(Ax+#u7imm)++Ak *Ax[#u7imm]++Ak addr = Ax + #u7imm, Ax = Ax + Ak (#u7imm = 0 to 128) 1 0 0 #u7imm Ak[0-3] Ax[0-14] 1
*(A15-#n13imm) *A15-[#n13imm] addr = A15 - #n13imm (#n13imm = 1 to 8192) 1 0 1 #n13imm
*(Ax++#u8imm) *Ax++[#u8imm] addr = Ax, Ax = Ax + #u8imm (#u8imm = 0 to 255 range) 1 1 0 0 #u8imm Ax[0-14] 1
*(Ax--#n8imm) *Ax--[#n8imm] addr = Ax, Ax = Ax - #n8imm (#n8imm = 1 to 256 range) 1 1 0 1 #n8imm Ax[0-14] 1
*(Ax-=#n8imm) *Ax-=[#n8imm] Ax = Ax - #n8imm, addr = Ax (#n8imm = 1 to 256 range) 1 1 1 0 #n8imm Ax[0-14] 1
*(Ax+Ak<<#u2imm) *Ax[Ak] addr = Ax + Ak << #u2imm (#u2imm = 0, 1, 2, 3) 1 1 1 1 #u2imm 1 1 1 1 Ak[0-3] Ax[0-14] 1
*(Aj=(Ax+Ak<<#u2imm)) *Aj=Ax[Ak] addr = Ax + Ak << #u2imm, Aj = addr (#u2imm = 0, 1, 2, 3) 1 1 1 1 #u2imm Aj[0-14] Ak[0-3] Ax[0-14] 1
(1) The Ax[0-14] addressing field can support the A15 register, however this is the stack pointer (SP) register and for some of the addressing modes, the operation is not valid for the SP and hence the addressing mode can not be used.
(2) Data Move operations have two ADDR1 fields, all other operations only have one ADDR1 field. Except for Data Move operations, the ADDR1 field is located in bits [31:16] of the instruction opcode.

The following are the instructions that can use the ADDR1 field:

ADD.32, ADD.S16, ADD.S8, AND.16, AND.8, AND.U16, AND.U8, ANDOR.B0, ANDOR.W0, LD.32, LD.64, LD.B0, LD.B1, LD.B2, LD.B3, LD.S16, LD.S8, LD.U16, LD.U8, LD.W0, LD.W1, MV.16, MV.32, MV.64, MV.8, MV.U16, MV.U8, OR.16, OR.8, RET{D}, S16TOF, ST.16, ST.32, ST.64, ST.8, ST.B0, ST.B1, ST.B2, ST.B3, ST.W0, ST.W1, SUB.32, SUB.S16, SUB.S8, SUBR.32, SUBR.S16, SUBR.S8, U16TOF, XOR.16, XOR.8

Examples:

; Load the 32-bit value in ADDR1 into Mx, using a base address + offset 
; (#u7imm) and then post increment by Ak (Ak is number of bytes to increment)
; NOTE: make sure 32-bit alignment of base address (Ax) and offset
LD.32 Mx,ADDR1              ; field
LD.32 Mx,*(Ax+#u7imm)++Ak   ; addressing mode
LD.32 M1,*(A14+#100)++A2    ; actual assembly code

; OR #x16 with the address pointed to by ADDR1, and store the result 
; into the location pointed to by ADDR1. Then post decrement the Ax register
; by the #n8imm value
; NOTE: make sure 16-bit alignment of base address (Ax) and offset
OR.16 ADDR1,#x16            ; field
OR.16 *Ax--[#n8imm],#x16    ; addressing mode
OR.16 *A3--[#70],#50110     ; actual assembly code