SPRUIY2A November   2024  – March 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating-Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
        1. 3.2.1.1 Required Instructions (RESET)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
        1. 3.2.2.1 Blocking and Masking (NMI)
        2. 3.2.2.2 Signal Propagation (NMI)
        3. 3.2.2.3 Stack (NMI)
        4. 3.2.2.4 Required Instructions (NMI)
      3. 3.2.3 RTINT (Real-Time Interrupt)
        1. 3.2.3.1 Blocking and Masking (RTINT)
        2. 3.2.3.2 Signal Propagation (RTINT)
        3. 3.2.3.3 Stack (RTINT)
        4. 3.2.3.4 Required Instructions (RTINT)
      4. 3.2.4 INT (Low-Priority Interrupt)
        1. 3.2.4.1 Blocking and Masking (INT)
        2. 3.2.4.2 Signal Propagation (INT)
        3. 3.2.4.3 Stack (INT)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Addressing Modes
    1. 4.1 Addressing Modes Overview
      1. 4.1.1 Documentation and Implementation
      2. 4.1.2 List of Addressing Mode Types
        1. 4.1.2.1 Additional Types of Addressing
      3. 4.1.3 Addressing Modes Summarized
    2. 4.2 Addressing Mode Fields
      1. 4.2.1 ADDR1 Field
      2. 4.2.2 ADDR2 Field
      3. 4.2.3 ADDR3 Field
      4. 4.2.4 DIRM Field
      5. 4.2.5 Additional Fields
    3. 4.3 Alignment and Pipeline Considerations
      1. 4.3.1 Alignment
      2. 4.3.2 Pipeline Considerations
    4. 4.4 Types of Addressing Modes
      1. 4.4.1 Direct Addressing
      2. 4.4.2 Pointer Addressing
        1. 4.4.2.1 Pointer Addressing with #Immediate Offset
        2. 4.4.2.2 Pointer Addressing with Pointer Offset
        3. 4.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 4.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 4.4.3 Stack Addressing
        1. 4.4.3.1 Allocating and De-allocating Stack Space
      4. 4.4.4 Circular Addressing Instruction
      5. 4.4.5 Bit Reversed Addressing Instruction
  7. 5Safety and Security Unit (SSU)
    1. 5.1 SSU Overview
    2. 5.2 Links and Task Isolation
    3. 5.3 Sharing Data Outside Task Isolation Boundary
    4. 5.4 Protected Call and Return
  8. 6Emulation
    1. 6.1 Overview of Emulation Features
    2. 6.2 Debug Terminology
    3. 6.3 Debug Interface
    4. 6.4 Execution Control Mode
    5. 6.5 Breakpoints, Watchpoints, and Counters
      1. 6.5.1 Software Breakpoint
      2. 6.5.2 Hardware Debugging Resources
        1. 6.5.2.1 Hardware Breakpoint
        2. 6.5.2.2 Hardware Watchpoint
        3. 6.5.2.3 Benchmark Counters
      3. 6.5.3 PC Trace
  9. 7Revision History

3.2.2.1 Blocking and Masking (NMI)

NMIs cannot be masked or blocked in the CPU. There is no global enable/disable bit for the NMI line in the CPU. Because of this, any interrupts that are received on the NMI line are directly passed to the CPU for prioritization. Priority is then decided amongst the interrupt types (NMI, RTINT, and INT lines). NMI always has highest priority and asserts within any RTINT or INT currently executing. ATOMIC instructions in RTINT or INT ISRs cannot block or prevent NMI from asserting. ATOMIC instructions have no effect on NMI.