SBASAX3A May   2025  – September 2025 ADS9326 , ADS9327

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics 
    6. 6.6  Electrical Characteristics: AVDD = 5V
    7. 6.7  Electrical Characteristics: AVDD = 3.3V
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Reference
        1. 7.3.2.1 Internal Reference
          1. 7.3.2.1.1 Selectable Internal Reference with 5V AVDD
        2. 7.3.2.2 External Reference
        3. 7.3.2.3 External Reference With External Reference Buffer
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Data Interface
      5. 7.3.5 Programmable Data Averaging Filter
        1. 7.3.5.1 Simple Average
          1. 7.3.5.1.1 Simple Average with Noncontinuous CONVST
        2. 7.3.5.2 Moving Average
      6. 7.3.6 CRC on Output Data Interface
      7. 7.3.7 ADC Output Data Randomizer
      8. 7.3.8 Data Frame Width
      9. 7.3.9 Daisy-Chain Mode
        1. 7.3.9.1 Daisy-Clock Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Low-Latency Mode
      4. 7.4.4 CS-CONVST Short Mode
      5. 7.4.5 Register Read Mode
      6. 7.4.6 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1 SPI Frame Length for Register Operations
      2. 7.5.2 Register Map Lock
      3. 7.5.3 Register Write
      4. 7.5.4 Register Read
  9. 8 Register Map: ADS9327
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
    3. 8.3 Register Bank 2
  10. 9 Register Map: ADS9326
    1. 9.1 Register Bank 0
    2. 9.2 Register Bank 1
    3. 9.3 Register Bank 2
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Analog 1VPP Sine-Cosine Encoder Interface
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

9.1 Register Bank 0

Table 9-42 lists the memory-mapped registers for the Register Bank 0 registers. All register offset addresses not listed in Table 9-42 must be considered as reserved locations and the register contents must not be modified.

Table 9-24 Register Map Bank 0
AddressAcronymBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x01Register 01hREG_READ_ADDR[7:0]
RESERVEDRESETDATA_SEL
0x02Register 02hRESERVED
RESERVEDREG_BANK_SEL[3:0]
0x03Register 03hRESERVED
RESERVEDBANK_2_UNLOCK[3:0]
0xFERegister FEhREG_LOCK[15:0]
REG_LOCK[15:0]

Complex bit access types are encoded to fit into small table cells. Table 9-43 shows the codes that are used for access types in this section.

Table 9-25 Register Bank 0 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1.1 Register 01h (Address = 0x01) [Reset = 0x0000]

Return to the Summary Table.

Figure 9-18 Register 01h
15141312111098
REG_READ_ADDR[7:0]
R/W-00000000b
76543210
RESERVEDRESETDATA_SEL
R/W-000000bR/W-0bR/W-0b
Table 9-26 Register 01h Field Descriptions
BitFieldTypeResetDescription
15:8REG_READ_ADDR[7:0]R/W00000000b8-bit address of the register to be read.
7:2RESERVEDR/W000000bReserved. Do not change from the default reset value.
1RESETR/W0bADC reset control.
  • 0b = Normal device operation.
  • 1b = Reset ADC and all registers
0DATA_SELR/W0bSelect data to be launched on serial interface of the ADC.
  • 0b = ADC conversion result is output.
  • 1b = Register data is output on D3.

8.1.2 Register 02h (Address = 0x02) [Reset = 0x0000]

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Figure 9-19 Register 02h
15141312111098
RESERVED
R/W-000000000000b
76543210
RESERVEDREG_BANK_SEL[3:0]
R/W-000000000000bR/W-0000b
Table 9-27 Register 02h Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR/W000000000000bReserved. Do not change from the default reset value.
3:0REG_BANK_SEL[3:0]R/W0000bRegister bank selection for read and write operations.
  • 0000b = Select register bank 0.
  • 0010b = Select register bank 1.
  • 1000b = Select register bank 2.

8.1.3 Register 03h (Address = 0x03) [Reset = 0x0000]

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Figure 9-20 Register 03h
15141312111098
RESERVED
R/W-000000000000b
76543210
RESERVEDBANK_2_UNLOCK[3:0]
R/W-000000000000bR/W-0000b
Table 9-28 Register 03h Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR/W000000000000bReserved. Do not change from the default reset value.
3:0BANK_2_UNLOCK[3:0]R/W0000bKey to unlock register bank 2.
  • 1011b = Unlock register bank 2.

8.1.4 Register FEh (Address = 0xFE) [Reset = 0x0000]

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Figure 9-21 Register FEh
15141312111098
REG_LOCK[15:0]
R/W-0000000000000000b
76543210
REG_LOCK[15:0]
R/W-0000000000000000b
Table 9-29 Register FEh Field Descriptions
BitFieldTypeResetDescription
15:0REG_LOCK[15:0]R/W0000000000000000bKey to unlock and lock the register map.
To unlock the register map, write 0xB38F followed by 0xABCD. To lock the register map, write 0x1234.