SBASAX3A May   2025  – September 2025 ADS9326 , ADS9327

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics 
    6. 6.6  Electrical Characteristics: AVDD = 5V
    7. 6.7  Electrical Characteristics: AVDD = 3.3V
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Reference
        1. 7.3.2.1 Internal Reference
          1. 7.3.2.1.1 Selectable Internal Reference with 5V AVDD
        2. 7.3.2.2 External Reference
        3. 7.3.2.3 External Reference With External Reference Buffer
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Data Interface
      5. 7.3.5 Programmable Data Averaging Filter
        1. 7.3.5.1 Simple Average
          1. 7.3.5.1.1 Simple Average with Noncontinuous CONVST
        2. 7.3.5.2 Moving Average
      6. 7.3.6 CRC on Output Data Interface
      7. 7.3.7 ADC Output Data Randomizer
      8. 7.3.8 Data Frame Width
      9. 7.3.9 Daisy-Chain Mode
        1. 7.3.9.1 Daisy-Clock Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Low-Latency Mode
      4. 7.4.4 CS-CONVST Short Mode
      5. 7.4.5 Register Read Mode
      6. 7.4.6 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1 SPI Frame Length for Register Operations
      2. 7.5.2 Register Map Lock
      3. 7.5.3 Register Write
      4. 7.5.4 Register Read
  9. 8 Register Map: ADS9327
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
    3. 8.3 Register Bank 2
  10. 9 Register Map: ADS9326
    1. 9.1 Register Bank 0
    2. 9.2 Register Bank 1
    3. 9.3 Register Bank 2
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Analog 1VPP Sine-Cosine Encoder Interface
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

9.2 Register Bank 1

Table 9-42 lists the memory-mapped registers for the Register Bank 1 registers. All register offset addresses not listed in Table 9-42 must be considered as reserved locations and the register contents must not be modified.

Table 9-7 Register Map Bank 1
AddressAcronymBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x08Register 08hRESERVED
RESERVEDPDN_CH[1:0]RESERVEDPDN_CTL
0x09Register 09hRESERVEDLATENCY_MODERESERVED
RESERVEDNUM_DATA_LANES[2:0]RESERVEDDAISY_CLK
0x0ARegister 0AhRESERVED
RESERVEDDIG_DELAY_ENDRIVE_STRENGTH[2:0]
0x0BRegister 0BhRESERVEDDIG_DELAY_D3[2:0]DIG_DELAY_D2[2:0]
DIG_DELAY_D2[2:0]DIG_DELAY_D1[2:0]DIG_DELAY_D0[2:0]
0x0CRegister 0ChRESERVEDPD_REF[1:0]
RESERVEDCLK_PWR[2:0]RESERVED
0x0DRegister 0DhXOR_EN[4:0]CRC_ENRESERVEDDATA_FORMAT
SAVG_MODE[3:0]RESERVEDAVG_SYNCSAVG_EN
0x0FRegister 0FhRESERVED
RESERVEDTEST_PATT_INCR[1:0]TEST_PATT_MODE[1:0]RESERVEDTEST_PATT_EN
0x10Register 10hTEST_PATT_1[15:0]
TEST_PATT_1[15:0]
0x11Register 11hTEST_PATT_2[15:0]
TEST_PATT_2[15:0]
0x13Register 13hRESERVEDCSZ_CONVST_SHORT_EN[2:0]
CSZ_CONVST_SHORT_EN[2:0]RESERVED

Complex bit access types are encoded to fit into small table cells. Table 9-43 shows the codes that are used for access types in this section.

Table 9-8 Register Bank 1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

9.2.1 Register 08h (Address = 0x08) [Reset = 0x0000]

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Figure 9-5 Register 08h
15141312111098
RESERVED
R/W-000000000000b
76543210
RESERVEDPDN_CH[1:0]RESERVEDPDN_CTL
R/W-000000000000bR/W-00bR/W-0bR/W-0b
Table 9-9 Register 08h Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR/W000000000000bReserved. Do not change from the default reset value.
3:2PDN_CH[1:0]R/W00bPower-down control for the analog input channels.
  • 00b = Normal device operation.
  • 01b = Channel A powered down.
  • 10b = Channel B powered down.
  • 11b = Both channels powered down.
1RESERVEDR/W0bReserved. Do not change from the default reset value.
0PDN_CTLR/W0bFull device power-down control
  • 0b = Normal device operation.
  • 1b = Full device power-down control.

9.2.2 Register 09h (Address = 0x09) [Reset = 0x0000]

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Figure 9-6 Register 09h
15141312111098
RESERVEDLATENCY_MODERESERVED
R/W-00000bR/W-0bR/W-000b
76543210
RESERVEDNUM_DATA_LANES[2:0]RESERVEDDAISY_CLK
R/W-000bR/W-000bR/W-000bR/W-0b
Table 9-10 Register 09h Field Descriptions
BitFieldTypeResetDescription
15:11RESERVEDR/W00000bReserved. Do not change from the default reset value.
10LATENCY_MODER/W0bControl to select latency mode.
  • 0b = Data corresponding to sample N - 1 is launched on CS falling edge during sample N frame.
  • 1b = Low latency mode is active. Data corresponding to sample N is launched on CS falling edge during sample N frame. CS high until tCONV (max).
9:7RESERVEDR/W000bReserved. Do not change from the default reset value.
6:4NUM_DATA_LANES[2:0]R/W000bControl to select the number of lanes used for the serial data interface.
  • 000b = ADC A data output on D[3:2] and ADC B data output on D[1:0].
  • 101b = ADC A data output on D3 and ADC B data output on D1. D2 and D0 are HI-Z.
  • 110b = ADC A and ADC B data output on D3. D[2:0] are HI-Z.
3:1RESERVEDR/W000bReserved. Do not change from the default reset value.
0DAISY_CLKR/W0bControl to feed-through SCLK (Pin 17) on D0 (Pin 16) when multiple devices are daisy-chained.
  • 0b = D0 outputs data as per the data interface configuration.
  • 1b = D0 feeds-through SCLK.

9.2.3 Register 0Ah (Address = 0x0A) [Reset = 0x0000]

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Figure 9-7 Register 0Ah
15141312111098
RESERVED
R/W-000000000000b
76543210
RESERVEDDIG_DELAY_ENDRIVE_STRENGTH[2:0]
R/W-000000000000bR/W-0bR/W-000b
Table 9-11 Register 0Ah Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR/W000000000000bReserved. Do not change from the default reset value.
3DIG_DELAY_ENR/W0bControl for digital delay on the output buffer path.
  • 0b = Normal device operation.
  • 1b = Digital delay on the output buffer path is enabled. The magnitude is controlled by DIG_DELAY_Dx fields in address 0Bh.
2:0DRIVE_STRENGTH[2:0]R/W000bControl to configure the drive strength of the digital output buffer.
  • 000b = Normal device operation.
  • 101b = 0.5x drive strength.
  • 110b = 2x drive strength.
  • 111b = 1.5x drive strength.

9.2.4 Register 0Bh (Address = 0x0B) [Reset = 0x0000]

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Figure 9-8 Register 0Bh
15141312111098
RESERVEDDIG_DELAY_D3[2:0]DIG_DELAY_D2[2:0]
R/W-0000bR/W-000bR/W-000b
76543210
DIG_DELAY_D2[2:0]DIG_DELAY_D1[2:0]DIG_DELAY_D0[2:0]
R/W-000bR/W-000bR/W-000b
Table 9-12 Register 0Bh Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0000bReserved. Do not change from the default reset value.
11:9DIG_DELAY_D3[2:0]R/W000bProgrammable digital delay on D3.
  • 000b = 0ns delay.
  • 001b = 1ns delay.
  • 010b = 2ns delay.
  • 011b = 3ns delay.
  • 100b = 4ns delay.
  • 101b = 5ns delay.
8:6DIG_DELAY_D2[2:0]R/W000bProgrammable digital delay on D2.
  • 000b = 0ns delay.
  • 001b = 1ns delay.
  • 010b = 2ns delay.
  • 011b = 3ns delay.
  • 100b = 4ns delay.
  • 101b = 5ns delay.
5:3DIG_DELAY_D1[2:0]R/W000bProgrammable digital delay on D1.
  • 000b = 0ns delay.
  • 001b = 1ns delay.
  • 010b = 2ns delay.
  • 011b = 3ns delay.
  • 100b = 4ns delay.
  • 101b = 5ns delay.
2:0DIG_DELAY_D0[2:0]R/W000bProgrammable digital delay on D0.
  • 000b = 0ns delay.
  • 001b = 1ns delay.
  • 010b = 2ns delay.
  • 011b = 3ns delay.
  • 100b = 4ns delay.
  • 101b = 5ns delay.

9.2.5 Register 0Ch (Address = 0x0C) [Reset = 0x0000]

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Figure 9-9 Register 0Ch
15141312111098
RESERVEDPD_REF[1:0]
R/W-000000bR/W-00b
76543210
RESERVEDCLK_PWR[2:0]RESERVED
R/W-0bR/W-000bR/W-0000b
Table 9-13 Register 0Ch Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:8PD_REF[1:0]R/W00bADC reference voltage source selection.
  • 10b = Internal reference is active.
  • 11b = Internal reference is inactive. Force an external reference via REFIO (pin 9).
7RESERVEDR/W0bReserved. Do not change from the default reset value.
6:4CLK_PWR[2:0]R/W000bControl to select the power supply domain for the input clock.
  • 000b = IOVDD domain.
  • 101b = VDD_1V8 domain.
3:0RESERVEDR/W0000bReserved. Do not change from the default reset value.

9.2.6 Register 0Dh (Address = 0x0D) [Reset = 0x0000]

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Figure 9-10 Register 0Dh
15141312111098
XOR_EN[4:0]CRC_ENRESERVEDDATA_FORMAT
R/W-00000bR/W-0bR/W-0bR/W-0b
76543210
SAVG_MODE[3:0]RESERVEDAVG_SYNCSAVG_EN
R/W-0000bR/W-00bR/W-0bR/W-0b
Table 9-14 Register 0Dh Field Descriptions
BitFieldTypeResetDescription
15:11XOR_EN[4:0]R/W00000bControl to enable XOR operation on the ADC conversion result.
  • 00000b = XOR operation is inactive.
  • 01111b = Bit-wise XOR operation on the ADC conversion result is active.
10CRC_ENR/W0bControl to enable CRC on the data interface.
  • 0b = CRC module is inactive.
  • 1b = CRC module is active.
9RESERVEDR/W0bReserved. Do not change from the default reset value.
8DATA_FORMATR/W0bControl to select the data format for the ADC conversion result.
  • 0b = Two's complement format.
  • 1b = Straight binary format.
7:4SAVG_MODE[3:0]R/W0000bControl for the number of samples to be averaged in simple averaging mode.
  • 0000b = 2 samples averaged.
  • 0001b = 4 samples averaged.
  • 0010b = 8 samples averaged.
  • 0011b = 16 samples averaged.
  • 0100b = 32 samples averaged.
  • 0101b = 64 samples averaged.
  • 0110b = 128 samples averaged.
3:2RESERVEDR/W00bReserved. Do not change from the default reset value.
1AVG_SYNCR/W0bSynchronization control for the internal averaging filter.
Write 1b to trigger when averaging must start from the subsequent cycle.
0SAVG_ENR/W0bControl to enable simple averaging. Select the number of samples to be averaged in SAVG_MODE.
  • 0b = Simple averaging is inactive.
  • 1b = Simple averaging is active.

9.2.7 Register 0Fh (Address = 0x0F) [Reset = 0x0000]

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Figure 9-11 Register 0Fh
15141312111098
RESERVED
R/W-0000000000b
76543210
RESERVEDTEST_PATT_INCR[1:0]TEST_PATT_MODE[1:0]RESERVEDTEST_PATT_EN
R/W-0000000000bR/W-00bR/W-00bR/W-0bR/W-0b
Table 9-15 Register 0Fh Field Descriptions
BitFieldTypeResetDescription
15:6RESERVEDR/W0000000000bReserved. Do not change from the default reset value.
5:4TEST_PATT_INCR[1:0]R/W00bIncrement value for the ramp pattern output.
  • 00b = 1024
  • 01b = 2048
  • 10b = 3072
  • 11b = 4096
3:2TEST_PATT_MODE[1:0]R/W00bType of test pattern at the data interface.
  • 00b = ADC outputs constant pattern defined in TEST_PATT_1 in address 0x10 and TEST_PATT_2 in address 0x11 for ADC A and ADC B respectively.
  • 01b = Ramp pattern.
  • 10b = Alternate pattern between AAAA and 5555 toggled at each readout.
1RESERVEDR/W0bReserved. Do not change from the default reset value.
0TEST_PATT_ENR/W0bControl to enable digital test pattern for data.
  • 0b = ADC conversion result is launched on the data interface.
  • 1b = Digital test pattern is launched on the data interface.

9.2.8 Register 10h (Address = 0x10) [Reset = 0x0000]

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Figure 9-12 Register 10h
15141312111098
TEST_PATT_1[15:0]
R/W-0000000000000000b
76543210
TEST_PATT_1[15:0]
R/W-0000000000000000b
Table 9-16 Register 10h Field Descriptions
BitFieldTypeResetDescription
15:0TEST_PATT_1[15:0]R/W0000000000000000b16-bit test pattern corresponding to ADC A.

9.2.9 Register 11h (Address = 0x11) [Reset = 0x0000]

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Figure 9-13 Register 11h
15141312111098
TEST_PATT_2[15:0]
R/W-0000000000000000b
76543210
TEST_PATT_2[15:0]
R/W-0000000000000000b
Table 9-17 Register 11h Field Descriptions
BitFieldTypeResetDescription
15:0TEST_PATT_2[15:0]R/W0000000000000000b16-bit test pattern corresponding to ADC B.

9.2.10 Register 13h (Address = 0x13) [Reset = 0x0000]

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Figure 9-14 Register 13h
15141312111098
RESERVEDCSZ_CONVST_SHORT_EN[2:0]
R/W-000000bR/W-000b
76543210
CSZ_CONVST_SHORT_EN[2:0]RESERVED
R/W-000bR/W-0000000b
Table 9-18 Register 13h Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:7CSZ_CONVST_SHORT_EN[2:0]R/W000bControl to enable CS-CONVST short mode.
  • 000b = Normal device operation.
  • 101b = CS-CONVST short mode is active.
6:0RESERVEDR/W0000000bReserved. Do not change from the default reset value.