SBASB61 August   2026 ADS114S18 , ADS124S18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Power-Scalable Speed Modes
      5. 7.3.5  Clock Source
      6. 7.3.6  Delta-Sigma Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Sinc3 and Sinc4 Filters
        2. 7.3.7.2 Sinc4 + Sinc1 Filter
        3. 7.3.7.3 FIR Filter
        4. 7.3.7.4 50Hz and 60Hz Line Cycle Rejection
        5. 7.3.7.5 Digital Filter Latency
        6. 7.3.7.6 Global-Chop Mode
      8. 7.3.8  Excitation Current Sources (IDACs)
      9. 7.3.9  Burn-Out Current Sources (BOCS)
      10. 7.3.10 Bias Voltage Generator (VBIAS)
      11. 7.3.11 General Purpose IOs (GPIOs)
        1. 7.3.11.1 ALERT Output
        2. 7.3.11.2 FAULT Output
      12. 7.3.12 Offset and Gain Calibration Coefficients
      13. 7.3.13 Digital Comparator
      14. 7.3.14 System Monitors
        1. 7.3.14.1 Internal Short (Offset Calibration)
        2. 7.3.14.2 Internal Temperature Sensor
        3. 7.3.14.3 External Reference Voltage Readback
        4. 7.3.14.4 Power-Supply Readback
      15. 7.3.15 Monitors and Status Flags
        1. 7.3.15.1 Reset (RESETn flag)
        2. 7.3.15.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.15.3 Reference Undervoltage Monitor (REF_UVn flag)
        4. 7.3.15.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.15.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.15.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.15.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.15.8 Digital Comparator Alert (COMP_ALERTn flag)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 RESET Pin
        3. 7.4.1.3 Reset by Register Write
        4. 7.4.1.4 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Sequencer Mode
          1. 7.4.2.3.1 Configuring the Sequencer
          2. 7.4.2.3.2 Starting and Stopping the Sequencer (START/STOP bits and START pin)
          3. 7.4.2.3.3 Sequencer Status Bits
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Register Map CRC
      11. 7.5.11 Conversion Data Format
  9. 8 Register Map
    1. 8.1 Status and General Configuration Page Registers
    2. 8.2 Step Configuration Page Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Interfacing With Multiple Devices
      4. 9.1.4 Device Initialization and Starting the Sequencer
      5. 9.1.5 Sequencer Configuration Strategy Example
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
      4. 9.2.4 Autonomous Power Supply Monitoring
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.1 Status and General Configuration Page Registers

Table 8-2 lists the memory-mapped registers for the Status and General Configuration Page Registers registers. All register offset addresses not listed in Table 8-2 should be considered as reserved locations and the register contents should not be modified.

Table 8-2 Register Map
AddressAcronymResetBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
ID Registers - not covered by register map CRC
00hDEVICE_IDXXhRESERVEDCH_CNT[1:0]DEV_ID[3:0]
01hREVISION_IDXXhREV_ID[7:0]
Status Registers (Aggregate Bits) - not covered by register map CRC
02hSTATUS_MSB00hSTEP_INDICATOR[4:0]SAD_FAULTnRESETnDRDY
03hSTATUS_LSBFFhCONV_COUNT[3:0]RESERVEDREG_WRITE_FAULTnSPI_CRC_FAULTn
Status Registers (Individual Bits) - not covered by register map CRC
04hSUPPLY_STATUSBFhRESERVEDAVDD_UVnRESERVED
05hADC_STATUSFFhCOMP_ALERTnRESERVEDREF_UVnRESERVED
06hDIGITAL_STATUSFFhMEM_FAULTnRESERVEDCRC_FAULT_PAGE[4:0]REG_MAP_CRC_FAULTn
07hCOMP_ALERT_STATUSFFhRESERVEDCOMP_ALERT_STEP_INDICATOR[4:0]
Status Register (GPIOs) - not covered by register map CRC
08hGPIO_DATA_INPUT00hGPIO7_DAT_INGPIO6_DAT_INGPIO5_DAT_INGPIO4_DAT_INGPIO3_DAT_INGPIO2_DAT_INGPIO1_DAT_INGPIO0_DAT_IN
Status Registers (Sequencer) - not covered by register map CRC
09hSEQ_STATUS07hSEQ_ACTIVESEQ_COUNT[3:0]RESERVED
0AhRESERVED00hRESERVED
Conversion Control and Reset Registers - not covered by register map CRC
0BhCONVERSION_CTRL00hSTARTSTEP_INIT[4:0]RESERVEDSTOP
0ChRESET00hRESET_CODE[7:0]
General Configuration Registers
10hADC_CFG00hRESERVEDREF_VALCLK_SELGC_ENSPEED_MODE[1:0]STBY_MODEPWDN
11hDIGITAL_CFG00hSPARE[4:0]STATUS_ENSDO_MODECONT_READ_EN
12hVBIAS00hVBIAS_AIN7VBIAS_AIN6VBIAS_AIN5VBIAS_AIN4VBIAS_AIN3VBIAS_AIN2VBIAS_AIN1VBIAS_AIN0
13hGPIO_CFG000hGPIO3_CFG[1:0]GPIO2_CFG[1:0]GPIO1_CFG[1:0]GPIO0_CFG[1:0]
14hGPIO_CFG100hGPIO7_CFG[1:0]GPIO6_CFG[1:0]GPIO5_CFG[1:0]GPIO4_CFG[1:0]
15hGPIO_CFG208hRESERVEDCOMP_ALERTn_MASKFAULT_PIN_BEHAVIORALERT_PIN_POLGPIO4_SRCGPIO3_SRC
16hMONITOR_CFG04hRESERVEDREF_UV_ENREF_UV_SELREG_MAP_CRC_ENSPI_CRC_EN
17hRESERVED00hRESERVED
18hSPARE00hSPARE[7:0]
Sequencer Configuration Registers
19hSEQUENCER_CFG50hSEQ_MODE[1:0]STOP_BEHAVIOR[1:0]RESERVED
1AhSEQUENCE_STEP_EN_001hSTEP_7_ENSTEP_6_ENSTEP_5_ENSTEP_4_ENSTEP_3_ENSTEP_2_ENSTEP_1_ENSTEP_0_EN
1BhSEQUENCE_STEP_EN_100hSTEP_15_ENSTEP_14_ENSTEP_13_ENSTEP_12_ENSTEP_11_ENSTEP_10_ENSTEP_9_ENSTEP_8_EN
1ChSEQUENCE_STEP_EN_200hSTEP_23_ENSTEP_22_ENSTEP_21_ENSTEP_20_ENSTEP_19_ENSTEP_18_ENSTEP_17_ENSTEP_16_EN
Reserved Registers
1DhRESERVED00hRESERVED
1EhRESERVED00hRESERVED
1FhRESERVED00hRESERVED
Register Map CRC Value Register
3DhREG_MAP_CRC00hGENERAL_CFG_REG_MAP_CRC_VALUE[7:0]
Page Indicator and Pointer Registers
3EhPAGE_INDICATOR00hPAGE_INDICATOR[7:0]
3FhPAGE_POINTER00hPAGE_POINTER[7:0]

Complex bit access types are encoded to fit into small table cells. Table 8-3 shows the codes that are used for access types in this section.

Table 8-3 Status and General Configuration Page Registers Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1.1 DEVICE_ID Register (Address = 00h) [Reset = XXh]

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Figure 8-1 DEVICE_ID Register
76543210
RESERVEDCH_CNT[1:0]DEV_ID[3:0]
R-00bR-xxbR-xxxxb
Table 8-4 DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR00bReserved
Always reads 00b.
5:4CH_CNT[1:0]RxxbChannel count
11b = 18 analog inputs
10b = 8 analog inputs
3:0DEV_ID[3:0]RxxxxbDevice ID
0010b = 16 bit
0011b = 24 bit

8.1.2 REVISION_ID Register (Address = 01h) [Reset = XXh]

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Figure 8-2 REVISION_ID Register
76543210
REV_ID[7:0]
R-xxxxxxxxb
Table 8-5 REVISION_ID Register Field Descriptions
BitFieldTypeResetDescription
7:0REV_ID[7:0]RxxxxxxxxbRevision ID
Values are subject to change without notice.

8.1.3 STATUS_MSB Register (Address = 02h) [Reset = 00h]

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Figure 8-3 STATUS_MSB Register
76543210
STEP_INDICATOR[4:0]SAD_FAULTnRESETnDRDY
R-00000bR-0bR/W-0bR-0b
Table 8-6 STATUS_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:3STEP_INDICATOR[4:0]R00000bSequence step indicator
Indicates the step page configuration that was used for the latest conversion result, which is currently available for readout. The step indicator resets to 00h after a device reset, in power-down mode, or when writing to the SEQUENCER_CFG register. At the same time the conversion counter (CONV_COUNT[3:0]) resets to Fh, the sequence counter (SEQ_COUNT[3:0]) resets to 0h, and the conversion data clears.
2SAD_FAULTnR0bSupply, ADC, and digital fault flag
Indicates if any of the individual fault flags in the SUPPLY_STATUS, ADC_STATUS, or DIGITAL_STATUS registers are set. For this bit to clear, all bits in the SUPPLY_STATUS, ADC_STATUS, and DIGITAL_STATUS registers must be cleared to 1b. The COMP_ALERTn bit can be masked from setting the SAD_FAULTn flag in case the COMP_ALERTn bit is 0b using the COMP_ALERTn_MASK bit.
  • 0b = Fault occurred
  • 1b = No fault occurred
1RESETnR/W0bReset flag
Indicates a device reset occurred. Write 1b to clear bit to 1b.
  • 0b = Reset occurred
  • 1b = No reset occurred
0DRDYR0bData-ready indication bit
The DRDY bit is the inverse of the DRDY pin. Enable the transmission of the STATUS header using the STATUS_EN bit to leverage the DRDY bit indication. The DRDY bit indicates if the conversion data read within the current SPI frame are new or are repeated data from the last read operation. Polling the DRDY bit using the register read command is not reliable, because the DRDY bit returns to 0b during the first frame of the read register command transmission already.
  • 0b = Data are not new
  • 1b = Data are new

8.1.4 STATUS_LSB Register (Address = 03h) [Reset = FFh]

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Figure 8-4 STATUS_LSB Register
76543210
CONV_COUNT[3:0]RESERVEDREG_WRITE_FAULTnSPI_CRC_FAULTn
R-1111bR-11bR-1bR-1b
Table 8-7 STATUS_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:4CONV_COUNT[3:0]R1111bConversion counter
The conversion counter increments every time a new conversion completes. After reaching a counter value of Fh, the counter rolls over to 0h with the completion of the next conversion. The counter only resets to Fh in power-down mode, after a device reset, or when writing to the SEQUENCER_CFG register. At the same time the sequence step indicator (STEP_INDICATOR[4:0]) resets to 00h, the sequence counter (SEQ_COUNT[3:0]) resets to 0h, and the conversion data clears. At the completion of the first conversion after reset, power-down, or after writing to the SEQUENCER_CFG register, the counter reads 0h. When SEQ_MODE[1:0] = 10b or 11b, the counter always reads 0h for the first conversion of a step. When SEQ_MODE[1:0] = 00b or 01b, the counter value does not return to 0h when conversions on a new step page configuration complete. Reset the counter to Fh by writing to the SEQUENCER_CFG register before starting a conversion with a new step page configuration if desired. When the conversion counter is output as part of the STATUS header (STATUS_EN = 1b), the devices make sure that the conversion counter value always matches to the ADC conversion result that is output in the same frame.
3:2RESERVEDR11bReserved
Always reads 11b.
1REG_WRITE_FAULTnR1bRegister write access fault flag
Indicates a write access to an invalid register address occurred during the last register write operation. This flag sets when an invalid register address is written to, and updates at the next register write command. Reading from an invalid register address does not set the flag, but can be detected from the address indication inside the SPI frame of the read command.
  • 0b = Fault occurred
  • 1b = No fault occurred
0SPI_CRC_FAULTnR1bSPI CRC fault flag
Indicates a SPI CRC fault occurred on SDI in the previous SPI frame. The execution of the command in the frame where the SPI CRC fault occurred is blocked. Instead, a no operation command is executed. Commands in following frames are not blocked. This bit updates in every new SPI frame based on the CRC result of the previous SPI frame. Enable the SPI CRC using the SPI_CRC_EN bit. In addition, enable the transmission of the STATUS header using the STATUS_EN bit to get notified about any SPI CRC faults.
  • 0b = Fault occurred
  • 1b = No fault occurred

8.1.5 SUPPLY_STATUS Register (Address = 04h) [Reset = BFh]

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Figure 8-5 SUPPLY_STATUS Register
76543210
RESERVEDAVDD_UVnRESERVED
R-1bR/W-0bR-111111b
Table 8-8 SUPPLY_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR1bReserved
Always reads 1b.
6AVDD_UVnR/W0bAVDD undervoltage fault flag
Indicates the AVDD supply voltage dropped below the AVDD undervoltage threshold. AVDD_UVn always sets to 0b when entering power-down mode even when the AVDD supply did not drop below the AVDD undervoltage threshold. Write 1b to clear bit to 1b.
  • 0b = Fault occurred
  • 1b = No fault occurred
5:0RESERVEDR111111bReserved
Always reads 111111b.

8.1.6 ADC_STATUS Register (Address = 05h) [Reset = FFh]

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Figure 8-6 ADC_STATUS Register
76543210
COMP_ALERTnRESERVEDREF_UVnRESERVED
R/W-1bR-11bR/W-1bR-1111b
Table 8-9 ADC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7COMP_ALERTnR/W1bDigital comparator alert flag
Indicates the digital comparator on one of the sequence steps tripped. The COMP_ALERT_STEP_INDICATOR[4:0] bit field indicates which sequence step caused the alert. Write 1b to clear bit to 1b. Clearing this bit also resets the ALERT output in case GPIO3 is configured as ALERT output. This flag contributes to the SAD_FAULTn unless COMP_ALERTn_MASK is set to 1b. This flag always drives the ALERT output, regardless of the state of COMP_ALERTn_MASK.
  • 0b = Alert occurred
  • 1b = No alert occurred
6:5RESERVEDR11bReserved
Always reads 11b.
4REF_UVnR/W1bReference voltage undervoltage fault flag
Indicates the reference voltage selected by the STEPx_REF_SEL[1:0] bits on a certain sequence step dropped below the selected reference undervoltage threshold. Enable the reference undervoltage monitor using the REF_UV_EN bit. Select the reference undervoltage threshold using the REF_UV_SEL bit. Write 1b to clear bit to 1b.
  • 0b = Fault occurred
  • 1b = No fault occurred
3:0RESERVEDR1111bReserved
Always reads 1111b.

8.1.7 DIGITAL_STATUS Register (Address = 06h) [Reset = FFh]

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Figure 8-7 DIGITAL_STATUS Register
76543210
MEM_FAULTnRESERVEDCRC_FAULT_PAGE[4:0]REG_MAP_CRC_FAULTn
R/W-1bR-1bR-11111bR/W-1b
Table 8-10 DIGITAL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7MEM_FAULTnR/W1bInternal memory fault flag
Indicates a memory map CRC fault in the internal memory occurred. Perform a power cycle or reset the device when the bit is 0b.
  • 0b = Fault occurred
  • 1b = No fault occurred
6RESERVEDR1bReserved
Always reads 1b.
5:1CRC_FAULT_PAGE[4:0]R11111bRegister map CRC fault page indicator
Indicates which register page shows a CRC error when the REG_MAP_CRC_FAULTn indicates a CRC fault. If multiple register pages have a CRC error, then the indicator points to the first register page address where a CRC error exists. When the CRC error on the page which was indicated by the CRC_FAULT_PAGE[4:0] bit field is corrected by providing a correct register map CRC value, and another CRC error on another register page exists, the CRC_FAULT_PAGE[4:0] bit field does not update automatically. After writing 1b to the REG_MAP_CRC_FAULTn bit field, the REG_MAP_CRC_FAULTn sets to 0b again, and the CRC_FAULT_PAGE[4:0] bit field points to the next remaining first page address which has a register map CRC error. This bit field clears to 11111b when the REG_MAP_CRC_FAULTn flag is cleared to 1b.
0REG_MAP_CRC_FAULTnR/W1bRegister map CRC fault flag
Indicates a register map CRC fault on the Status and General Configuration page (register address space from 10h to 1Fh) or on any of the Step Configuration pages (register addresses 00h to 14h) occurred. Enable the register map CRC using the REG_MAP_CRC_EN bit. Write 1b to clear bit to 1b.
  • 0b = Fault occurred
  • 1b = No fault occurred

8.1.8 COMP_ALERT_STATUS Register (Address = 07h) [Reset = FFh]

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Figure 8-8 COMP_ALERT_STATUS Register
76543210
RESERVEDCOMP_ALERT_STEP_INDICATOR[4:0]
R-111bR-11111b
Table 8-11 COMP_ALERT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR111bReserved
Always reads 111b.
4:0COMP_ALERT_STEP_INDICATOR[4:0]R11111bDigital comparator alert step indicator
Indicates which sequence step had a comparator overrange condition when the COMP_ALERTn flag is set. Bits clear to 11111b when the COMP_ALERTn bit is cleared to 1b.

8.1.9 GPIO_DATA_INPUT Register (Address = 08h) [Reset = 00h]

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Figure 8-9 GPIO_DATA_INPUT Register
76543210
GPIO7_DAT_INGPIO6_DAT_INGPIO5_DAT_INGPIO4_DAT_INGPIO3_DAT_INGPIO2_DAT_INGPIO1_DAT_INGPIO0_DAT_IN
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 8-12 GPIO_DATA_INPUT Register Field Descriptions
BitFieldTypeResetDescription
7GPIO7_DAT_INR0bGPIO7 data
Read back value of GPIO7 when configured as digital input or output. Bit reads 0b when the GPIO function is disabled (GPIO7_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High
6GPIO6_DAT_INR0bGPIO6 data
Read back value of GPIO6 when configured as digital input or output. Bit reads 0b when the GPIO function is disabled (GPIO6_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High
5GPIO5_DAT_INR0bGPIO5 data
Read back value of GPIO5 when configured as digital input or output. Bit reads 0b when the GPIO function is disabled (GPIO5_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High
4GPIO4_DAT_INR0bGPIO4 data
Read back value of GPIO4 when configured as digital input, digital output, or static FAULT output. Bit reads 0b when the GPIO function is disabled (GPIO4_CFG[1:0] = 00b) or when GPIO4 is configured as FAULT output with heart beat function (GPIO4_CFG[1:0] = 10b or 11b, GPIO4_SRC = 1b, FAULT_PIN_BEHAVIOR = 1b).
  • 0b = Low
  • 1b = High
3GPIO3_DAT_INR0bGPIO3 data
Read back value of GPIO3 when configured as digital input, digital output, or ALERT output. Bit reads 0b when the GPIO function is disabled (GPIO3_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High
2GPIO2_DAT_INR0bGPIO2 data
Read back value of GPIO2 when configured as digital input or output. Bit reads 0b when the GPIO function is disabled (GPIO2_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High
1GPIO1_DAT_INR0bGPIO1 data
Read back value of GPIO1 when configured as digital input or output. Bit reads 0b when the GPIO function is disabled (GPIO1_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High
0GPIO0_DAT_INR0bGPIO0 data
Read back value of GPIO0 when configured as digital input or output. Bit reads 0b when the GPIO function is disabled (GPIO0_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High

8.1.10 SEQ_STATUS Register (Address = 09h) [Reset = 07h]

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Figure 8-10 SEQ_STATUS Register
76543210
SEQ_ACTIVESEQ_COUNT[3:0]RESERVED
R-0bR-0000bR-111b
Table 8-13 SEQ_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7SEQ_ACTIVER0bSequencer active flag
Indicates if conversions are currently ongoing or if conversions stopped and the device is in idle, standby or power-down mode.
  • 0b = Sequencer not active; no conversions ongoing
  • 1b = Sequencer active; conversions ongoing
6:3SEQ_COUNT[3:0]R0000bSequence counter
When SEQ_MODE[1:0] = 11b, the sequence counter indicates which sequence run the latest conversion result belongs to, which is currently available for readout. The sequence counter increments with the completion of the first conversion of a new sequence run. At the completion of the first conversion of the first sequence run, the counter reads 0h. At the completion of the first conversion of the second sequence run, the counter reads 1h. After reaching a counter value of Fh, the counter rolls over to 0h with the completion of the first conversion of the next sequence run. The counter resets to 0h at the completion of the first conversion after setting the START bit to 1b or at the rising edge of the START pin. When writing to the SEQUENCER_CFG register, in power-down mode, or after a device reset, the counter resets to 0h immediately. At the same time the sequence step indicator (STEP_INDICATOR[4:0]) resets to 00h, the conversion counter (CONV_COUNT[3:0]) resets to Fh, and the conversion data clears. The sequence counter always reads 0h when SEQ_MODE[1:0] = 00b, 01b, or 10b.
2:0RESERVEDR111bReserved
Always reads 111b.

8.1.11 CONVERSION_CTRL Register (Address = 0Bh) [Reset = 00h]

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Figure 8-11 CONVERSION_CTRL Register
76543210
STARTSTEP_INIT[4:0]RESERVEDSTOP
R/W-0bR/W-00000bR-0bR/W-0b
Table 8-14 CONVERSION_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7STARTR/W0bStart or re-start ADC conversions
Write 1b to start or re-start conversions using the step configuration page indicated in the STEP_INIT[4:0] bit field. The SEQ_MODE[1:0] bits determine the conversion and sequencer behavior. Writing 1b to both the START and STOP bits has no effect. The START bit is self-clearing and always reads 0b.
  • 0b = No operation
  • 1b = Start or restart conversions
6:2STEP_INIT[4:0]R/W00000bInitial execution step selector
Determines the sequence step configuration the sequencer selects for the first conversion when setting the START bit to 1b, or when taking the START pin high. If STEP_INIT[4:0] is set to a value between 18h and 1Fh, no conversion or sequence is started. The STEP_INIT[4:0] bit field also determines the step configuration page that is used whenever the device is in idle or standby mode, regardless if the respective step page is enabled or not (STEP_x_EN bit setting is ignored). That means, when coming out of power-down mode, or when conversions stop, the device transitions to the step page configuration determined by the STEP_INIT[4:0] bit field. If STEP_INIT[4:0] is set to a value between 18h and 1Fh in standby or idle mode, then the configuration of step 23 takes effect.
1RESERVEDR0bReserved
Always reads 0b.
0STOPR/W0bStop ADC conversions
Write 1b to stop conversions. The STOP_BEHAVIOR[1:0] bits determine the stopping behavior. Writing 1b to both the START and STOP bits has no effect. The STOP bit clears to 0b after conversions stopped or when the START bit is set before the ongoing conversions stopped.
  • 0b = No operation
  • 1b = Stop conversions

8.1.12 RESET Register (Address = 0Ch) [Reset = 00h]

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Figure 8-12 RESET Register
76543210
RESET_CODE[7:0]
R/W-00000000b
Table 8-15 RESET Register Field Descriptions
BitFieldTypeResetDescription
7:0RESET_CODE[7:0]R/W00000000bDevice reset register
Write 01011010b to reset the ADC. These bits always read 00000000b.

8.1.13 ADC_CFG Register (Address = 10h) [Reset = 00h]

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Figure 8-13 ADC_CFG Register
76543210
RESERVEDREF_VALCLK_SELGC_ENSPEED_MODE[1:0]STBY_MODEPWDN
R-0bR/W-0bR/W-0bR/W-0bR/W-00bR/W-0bR/W-0b
Table 8-16 ADC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved
Always reads 0b.
6REF_VALR/W0bInternal reference voltage value selection
Selects the voltage of the internal reference. The internal voltage reference is always enabled.
  • 0b = 1.25V
  • 1b = 2.5V
5CLK_SELR/W0bClock selection
Selects the clock source for the device.
  • 0b = Internal oscillator
  • 1b = External clock provided at the CLK pin
4GC_ENR/W0bGlobal-chop mode enable
Enables global-chop mode. When enabled, the device automatically swaps the analog inputs and takes the average of two consecutive conversions to cancel the internal offset voltage.
  • 0b = Disabled
  • 1b = Enabled
3:2SPEED_MODE[1:0]R/W00bSpeed mode selection
Selects the speed mode for the device.
  • 00b = Speed mode 0 (fMOD = 32kHz)
  • 01b = Speed mode 1 (fMOD = 256kHz)
  • 10b = Speed mode 2 (fMOD = 512kHz)
  • 11b = Speed mode 3 (fMOD = 1024kHz)
1STBY_MODER/W0bStandby mode selection
This bit enables the auto engagement of the low-power standby mode after conversions are stopped.
  • 0b = Idle mode; device remains fully powered when conversions stop.
  • 1b = Standby mode; device transitions to a low-power standby mode when conversions stop. Standby mode is exited when conversions restart.
0PWDNR/W0bPower-down mode selection
Powers down all circuitry except for circuitry necessary to retain the user register settings. SPI communication is still possible. In power-down mode, the step indicator (STEP_INDICATOR[4:0]) resets to 00h, the conversion counter (CONV_COUNT[3:0]) resets to Fh, the sequence counter (SEQ_COUNT[3:0]) resets to 0h, the conversion data clears, and the START bit and START pin are ignored. Setting the PWDN bit to 1b powers the device down immediately; any ongoing conversions are aborted. Any analog inputs configured as GPIO digital outputs transition into a Hi-Z state in power-down mode. To maintain a certain logic level during power-down, consider external pullup or pulldown resistors on the respective GPIO pins.
  • 0b = Active mode
  • 1b = Power-down mode

8.1.14 DIGITAL_CFG Register (Address = 11h) [Reset = 00h]

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Figure 8-14 DIGITAL_CFG Register
76543210
SPARE[4:0]STATUS_ENSDO_MODECONT_READ_EN
R/W-00000bR/W-0bR/W-0bR/W-0b
Table 8-17 DIGITAL_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:3SPARE[4:0]R/W00000bSpare register bits
Provided as R/W bits as a means to check the register map CRC. Bit settings have no effect.
2STATUS_ENR/W0bSTATUS header output enable
Enables the STATUS header (STATUS_MSB + STATUS_LSB registers) transmission on SDO as the first two bytes of every SPI frame.
  • 0b = Disabled
  • 1b = Enabled
1SDO_MODER/W0bSDO/DRDY mode selection
Selects the mode of the SDO/DRDY pin to either data-output function only, or to dual-mode function of data output and data ready. Use the data-output only mode when operating the device in a daisy chain.
  • 0b = Data-output only mode
  • 1b = Dual mode: data output and data ready
0CONT_READ_ENR/W0bContinuous-read mode enable
Enables continuous-read mode to allow reading multiple consecutive registers within a single SPI frame in 4-wire SPI mode. Disable continuous-read mode when operating the device in a daisy chain or in 3-wire SPI mode.
  • 0b = Disabled
  • 1b = Enabled

8.1.15 VBIAS Register (Address = 12h) [Reset = 00h]

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Figure 8-15 VBIAS Register
76543210
VBIAS_AIN7VBIAS_AIN6VBIAS_AIN5VBIAS_AIN4VBIAS_AIN3VBIAS_AIN2VBIAS_AIN1VBIAS_AIN0
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-18 VBIAS Register Field Descriptions
BitFieldTypeResetDescription
7VBIAS_AIN7R/W0bAIN7 VBIAS selection
Enables VBIAS on the AIN7 pin.
  • 0b = Disabled
  • 1b = Enabled
6VBIAS_AIN6R/W0bAIN6 VBIAS selection
Enables VBIAS on the AIN6 pin.
  • 0b = Disabled
  • 1b = Enabled
5VBIAS_AIN5R/W0bAIN5 VBIAS selection
Enables VBIAS on the AIN5 pin.
  • 0b = Disabled
  • 1b = Enabled
4VBIAS_AIN4R/W0bAIN4 VBIAS selection
Enables VBIAS on the AIN4 pin.
  • 0b = Disabled
  • 1b = Enabled
3VBIAS_AIN3R/W0bAIN3 VBIAS selection
Enables VBIAS on the AIN3 pin.
  • 0b = Disabled
  • 1b = Enabled
2VBIAS_AIN2R/W0bAIN2 VBIAS selection
Enables VBIAS on the AIN2 pin.
  • 0b = Disabled
  • 1b = Enabled
1VBIAS_AIN1R/W0bAIN1 VBIAS selection
Enables VBIAS on the AIN1 pin.
  • 0b = Disabled
  • 1b = Enabled
0VBIAS_AIN0R/W0bAIN0 VBIAS selection
Enables VBIAS on the AIN0 pin.
  • 0b = Disabled
  • 1b = Enabled

8.1.16 GPIO_CFG0 Register (Address = 13h) [Reset = 00h]

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Figure 8-16 GPIO_CFG0 Register
76543210
GPIO3_CFG[1:0]GPIO2_CFG[1:0]GPIO1_CFG[1:0]GPIO0_CFG[1:0]
R/W-00bR/W-00bR/W-00bR/W-00b
Table 8-19 GPIO_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7:6GPIO3_CFG[1:0]R/W00bGPIO3 configuration
Configures the GPIO3 pin behavior.
  • 00b = ADS1x4S18: Pin operates as analog input. ADS1x4S14: Pin is High-Z.
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
5:4GPIO2_CFG[1:0]R/W00bGPIO2 configuration
Configures the GPIO2 pin behavior.
  • 00b = ADS1x4S18: Pin operates as analog input. ADS1x4S14: Pin is High-Z.
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
3:2GPIO1_CFG[1:0]R/W00bGPIO1 configuration
Configures the GPIO1 pin behavior.
  • 00b = ADS1x4S18: Pin operates as analog input. ADS1x4S14: Pin is High-Z.
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
1:0GPIO0_CFG[1:0]R/W00bGPIO0 configuration
Configures the GPIO0 pin behavior.
  • 00b = ADS1x4S18: Pin operates as analog input. ADS1x4S14: Pin is High-Z.
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)

8.1.17 GPIO_CFG1 Register (Address = 14h) [Reset = 00h]

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Figure 8-17 GPIO_CFG1 Register
76543210
GPIO7_CFG[1:0]GPIO6_CFG[1:0]GPIO5_CFG[1:0]GPIO4_CFG[1:0]
R/W-00bR/W-00bR/W-00bR/W-00b
Table 8-20 GPIO_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7:6GPIO7_CFG[1:0]R/W00bGPIO7 configuration
Configures the GPIO7 pin behavior.
  • 00b = ADS1x4S18: Pin operates as analog or REFN1 input. ADS1x4S14: Pin operates as REFN1 input.
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
5:4GPIO6_CFG[1:0]R/W00bGPIO6 configuration
Configures the GPIO6 pin behavior.
  • 00b = ADS1x4S18: Pin operates as analog or REFP1 input. ADS1x4S14: Pin operates as REFP1 input.
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
3:2GPIO5_CFG[1:0]R/W00bGPIO5 configuration
Configures the GPIO5 pin behavior.
  • 00b = ADS1x4S18: Pin operates as analog input. ADS1x4S14: Pin is High-Z.
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
1:0GPIO4_CFG[1:0]R/W00bGPIO4 configuration
Configures the GPIO4 pin behavior.
  • 00b = ADS1x4S18: Pin operates as analog input. ADS1x4S14: Pin is High-Z.
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)

8.1.18 GPIO_CFG2 Register (Address = 15h) [Reset = 08h]

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Figure 8-18 GPIO_CFG2 Register
76543210
RESERVEDCOMP_ALERTn_MASKFAULT_PIN_BEHAVIORALERT_PIN_POLGPIO4_SRCGPIO3_SRC
R-000bR/W-0bR/W-1bR/W-0bR/W-0bR/W-0b
Table 8-21 GPIO_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR000bReserved
Always reads 0000b.
4COMP_ALERTn_MASKR/W0bComparator alert mask
Determines whether the COMP_ALERTn contributes to the SAD_FAULTn or not. When GPIO3 is configured as ALERT output, COMP_ALERTn triggers the ALERT pin regardless of the status of this mask bit.
  • 0b = Mask disabled. COMP_ALERTn triggers SAD_FAULTn.
  • 1b = Mask enabled. COMP_ALERTn does not trigger SAD_FAULTn, but still triggers ALERT pin.
3FAULT_PIN_BEHAVIORR/W1bFAULT pin behavior selection
Selects the behavior of the FAULT pin, when GPIO4 is configured as FAULT output (GPIO4_CFG[1:0] = 10b or 11b, GPIO4_SRC = 1b).
  • 0b = Static. Output is low when a fault occurred, otherwise output is high.
  • 1b = Heart beat. Output is low when a fault occurred, otherwise output is a 50% duty-cycle signal with a frequency of fMOD/256.
2ALERT_PIN_POLR/W0bALERT pin polarity selection
Selects the polarity of the ALERT output pin, when GPIO3 is configured as ALERT output (GPIO3_CFG[1:0] = 10b or 11b, GPIO3_SRC = 1b).
  • 0b = Active low
  • 1b = Active high
1GPIO4_SRCR/W0bGPIO4 data source selection
Selects the data source of the GPIO4 pin when GPIO4 is configured as digital output. The FAULT pin is low when the SAD_FAULTn flag is 0b.
  • 0b = GPIO4_DAT_OUT bit
  • 1b = SAD_FAULTn flag. Pin acts as FAULT output.
0GPIO3_SRCR/W0bGPIO3 data source selection
Selects the data source of the GPIO3 pin when GPIO3 is configured as digital output.
  • 0b = GPIO3_DAT_OUT bit
  • 1b = COMP_ALERTn flag. Pin acts as digital comparator ALERT output.

8.1.19 MONITOR_CFG Register (Address = 16h) [Reset = 04h]

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Figure 8-19 MONITOR_CFG Register
76543210
RESERVEDRESERVEDREF_UV_ENREF_UV_SELREG_MAP_CRC_ENSPI_CRC_EN
R-000bR/W-0bR/W-0bR/W-1bR/W-0bR/W-0b
Table 8-22 MONITOR_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR000bReserved
Always reads 000b.
4RESERVEDR/W0bReserved
Always write 0b.
3REF_UV_ENR/W0bReference undervoltage monitor enable
Enables the voltage reference monitor to detect when the selected voltage reference using the STEPx_REF_SEL[1:0] bits on a certain sequence step drops below the undervoltage monitor threshold.
  • 0b = Disabled
  • 1b = Enabled
2REF_UV_SELR/W1bVoltage reference undervoltage monitor threshold selection
Selects the voltage reference undervoltage monitor threshold.
  • 0b = 550 mV
  • 1b = 1 V
1REG_MAP_CRC_ENR/W0bRegister map CRC enable
Enables the register map CRC for the Status and General Configuration page (register addresses 10h to 1Fh) and the Step Configuration pages (register addresses 00h to 14h).
  • 0b = Disabled
  • 1b = Enabled
0SPI_CRC_ENR/W0bSPI CRC enable
Enables the SPI CRC on SDI and SDO.
  • 0b = Disabled
  • 1b = Enabled

8.1.20 SPARE Register (Address = 18h) [Reset = 00h]

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Figure 8-20 SPARE Register
76543210
SPARE[7:0]
R/W-00000000b
Table 8-23 SPARE Register Field Descriptions
BitFieldTypeResetDescription
7:0SPARE[7:0]R/W00000000bSpare register bits
Provided as R/W bits as a means to check the register map CRC. Bit settings have no effect.

8.1.21 SEQUENCER_CFG Register (Address = 19h) [Reset = 50h]

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Figure 8-21 SEQUENCER_CFG Register
76543210
SEQ_MODE[1:0]STOP_BEHAVIOR[1:0]RESERVEDRESERVED
R/W-01bR/W-01bR-00bR/W-00b
Table 8-24 SEQUENCER_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:6SEQ_MODE[1:0]R/W01bSequencer mode selection
Selects the operating mode of the sequencer. When STEP_INIT[4:0] is set to a value between 18h and 1Fh no conversion or sequence is started in any of the sequencer modes.
  • 00b = Execute the sequence step defined by the STEP_INIT[4:0] pointer one time. Step enable bits (STEP_x_EN) are ignored in this sequencer mode. The STEPx_NUM_CONV[4:0] bits determine the number of consecutive conversions for this sequence step.
  • 01b = Continuously convert the sequence step defined by the STEP_INIT[4:0] pointer. Step enable bits (STEP_x_EN) and STEPx_NUM_CONV[4:0] bits are ignored in this sequencer mode.
  • 10b = Execute a sequence of all enabled steps between the step defined by the STEP_INIT[4:0] pointer and step 23 one time. Use the STEP_x_EN bits to include a step in the sequence. The sequence does not execute if the step defined by the STEP_INIT[4:0] pointer is disabled.
  • 11b = Execute the sequence of all enabled steps and repeat the sequence continuously, starting with the step defined by the STEP_INIT[4:0] pointer. Use the STEP_x_EN bits to include a step in the sequence. The sequence does not execute if the step defined by the STEP_INIT[4:0] pointer is disabled.
5:4STOP_BEHAVIOR[1:0]R/W01bSequence stop behavior selection
Selects the device behavior when setting the STOP bit to 1b or when a falling edge on the START pin occurs.
  • 00b = Stop immediately. Any ongoing conversion is aborted.
  • 01b = Stop after current conversion completes.
  • 10b = Stop after current sequence step completes. If SEQ_MODE[1:0] = 01b when using this mode, then stop after current conversion completes.
  • 11b = Stop after full sequence completes. If SEQ_MODE[1:0] = 00b when using this mode, then stop after current sequence step completes. If SEQ_MODE[1:0] = 01b when using this mode, then stop after current conversion completes.
3:2RESERVEDR00bReserved
Always reads 00b.
1:0RESERVEDR/W00bReserved
Always write 00b.

8.1.22 SEQUENCE_STEP_EN_0 Register (Address = 1Ah) [Reset = 01h]

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Figure 8-22 SEQUENCE_STEP_EN_0 Register
76543210
STEP_7_ENSTEP_6_ENSTEP_5_ENSTEP_4_ENSTEP_3_ENSTEP_2_ENSTEP_1_ENSTEP_0_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-1b
Table 8-25 SEQUENCE_STEP_EN_0 Register Field Descriptions
BitFieldTypeResetDescription
7STEP_7_ENR/W0bSequencer step 7 enable
  • 0b = Step disabled
  • 1b = Step enabled
6STEP_6_ENR/W0bSequencer step 6 enable
  • 0b = Step disabled
  • 1b = Step enabled
5STEP_5_ENR/W0bSequencer step 5 enable
  • 0b = Step disabled
  • 1b = Step enabled
4STEP_4_ENR/W0bSequencer step 4 enable
  • 0b = Step disabled
  • 1b = Step enabled
3STEP_3_ENR/W0bSequencer step 3 enable
  • 0b = Step disabled
  • 1b = Step enabled
2STEP_2_ENR/W0bSequencer step 2 enable
  • 0b = Step disabled
  • 1b = Step enabled
1STEP_1_ENR/W0bSequencer step 1 enable
  • 0b = Step disabled
  • 1b = Step enabled
0STEP_0_ENR/W1bSequencer step 0 enable
  • 0b = Step disabled
  • 1b = Step enabled

8.1.23 SEQUENCE_STEP_EN_1 Register (Address = 1Bh) [Reset = 00h]

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Figure 8-23 SEQUENCE_STEP_EN_1 Register
76543210
STEP_15_ENSTEP_14_ENSTEP_13_ENSTEP_12_ENSTEP_11_ENSTEP_10_ENSTEP_9_ENSTEP_8_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-26 SEQUENCE_STEP_EN_1 Register Field Descriptions
BitFieldTypeResetDescription
7STEP_15_ENR/W0bSequencer step 15 enable
  • 0b = Step disabled
  • 1b = Step enabled
6STEP_14_ENR/W0bSequencer step 14 enable
  • 0b = Step disabled
  • 1b = Step enabled
5STEP_13_ENR/W0bSequencer step 13 enable
  • 0b = Step disabled
  • 1b = Step enabled
4STEP_12_ENR/W0bSequencer step 12 enable
  • 0b = Step disabled
  • 1b = Step enabled
3STEP_11_ENR/W0bSequencer step 11 enable
  • 0b = Step disabled
  • 1b = Step enabled
2STEP_10_ENR/W0bSequencer step 10 enable
  • 0b = Step disabled
  • 1b = Step enabled
1STEP_9_ENR/W0bSequencer step 9 enable
  • 0b = Step disabled
  • 1b = Step enabled
0STEP_8_ENR/W0bSequencer step 8 enable
  • 0b = Step disabled
  • 1b = Step enabled

8.1.24 SEQUENCE_STEP_EN_2 Register (Address = 1Ch) [Reset = 00h]

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Figure 8-24 SEQUENCE_STEP_EN_2 Register
76543210
STEP_23_ENSTEP_22_ENSTEP_21_ENSTEP_20_ENSTEP_19_ENSTEP_18_ENSTEP_17_ENSTEP_16_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-27 SEQUENCE_STEP_EN_2 Register Field Descriptions
BitFieldTypeResetDescription
7STEP_23_ENR/W0bSequencer step 23 enable
  • 0b = Step disabled
  • 1b = Step enabled
6STEP_22_ENR/W0bSequencer step 22 enable
  • 0b = Step disabled
  • 1b = Step enabled
5STEP_21_ENR/W0bSequencer step 21 enable
  • 0b = Step disabled
  • 1b = Step enabled
4STEP_20_ENR/W0bSequencer step 20 enable
  • 0b = Step disabled
  • 1b = Step enabled
3STEP_19_ENR/W0bSequencer step 19 enable
  • 0b = Step disabled
  • 1b = Step enabled
2STEP_18_ENR/W0bSequencer step 18 enable
  • 0b = Step disabled
  • 1b = Step enabled
1STEP_17_ENR/W0bSequencer step 17 enable
  • 0b = Step disabled
  • 1b = Step enabled
0STEP_16_ENR/W0bSequencer step 16 enable
  • 0b = Step disabled
  • 1b = Step enabled

8.1.25 REG_MAP_CRC Register (Address = 3Dh) [Reset = 00h]

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Figure 8-25 REG_MAP_CRC Register
76543210
GENERAL_CFG_REG_MAP_CRC_VALUE[7:0]
R/W-00000000b
Table 8-28 REG_MAP_CRC Register Field Descriptions
BitFieldTypeResetDescription
7:0GENERAL_CFG_REG_MAP_CRC_VALUE[7:0]R/W00000000bRegister map CRC value for the Status and General Configuration page
This value is the user-calculated CRC value of registers 10h to 1Fh.

8.1.26 PAGE_INDICATOR Register (Address = 3Eh) [Reset = 00h]

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Figure 8-26 PAGE_INDICATOR Register
76543210
PAGE_INDICATOR[7:0]
R-00000000b
Table 8-29 PAGE_INDICATOR Register Field Descriptions
BitFieldTypeResetDescription
7:0PAGE_INDICATOR[7:0]R00000000bRegister page indicator
Read the register page indicator to verify the register page which is currently selected for reading and writing registers.

8.1.27 PAGE_POINTER Register (Address = 3Fh) [Reset = 00h]

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Figure 8-27 PAGE_POINTER Register
76543210
PAGE_POINTER[7:0]
R/W-00000000b
Table 8-30 PAGE_POINTER Register Field Descriptions
BitFieldTypeResetDescription
7:0PAGE_POINTER[7:0]R/W00000000bRegister page pointer
Write the register page pointer to select the desired register page for reading and writing registers.