The circuit in Figure 9-5 employs a ratiometric measurement configuration. In other words, the sensor signal (that is, the voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same excitation source. Therefore, errors resulting from temperature drift or noise of the excitation source cancel because these errors are common to both the sensor signal and the reference.

To implement a ratiometric RTD measurement using the device, route IDAC1 to either AIN1 (for a 4-wire RTD connection) or to AIN0 (for 2- and 3-wire RTD connections) using the STEPx_I1MUX[4:0] bits. Select the excitation current source value using the STEPx_IUNIT and STEPx_I1MAG[3:0] bits. The excitation current flows through the RTD and a precision, low-drift reference resistor, R_REF to ground. The voltage, V_REF, generated across the reference resistor (as shown in Equation 21) is used as the ADC reference voltage. For that purpose, select the external voltage reference between pins REFP1 and REFN1 using the STEPx_REF_SEL[1:0] bits.

To simplify the following discussion, the individual lead resistance values of the RTDs (R_LEADx) are set to zero. As Equation 22 shows, IDAC1 excites the RTD to produce a voltage (V_RTD) proportional to the temperature-dependent RTD value and the IDAC1 value.

Select the analog inputs using the STEPx_AINP[4:0] and STEPx_AINN[4:0] bits to measure V_RTD based on the RTD type:

• For a 2-wire RTD, measure between AIN_P = AIN3 and AIN_N = AIN6.
• For a 3- or 4-wire RTD, measure between AIN_P = AIN3 and AIN_N = AIN4.

The device internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage against the reference voltage to produce a digital output code according to Equation 23.

Where n depends on the selected coding scheme and the ADC resolution:

• n = 15 (16 bit ADC, binary two's complement format)
• n = 16 (16 bit ADC, unipolar straight binary format)
• n = 23 (24 bit ADC, binary two's complement format)
• n = 24 (24 bit ADC, unipolar straight binary format)

As shown in Equation 24, the output code only depends on the value of the RTD, the PGA gain, and the reference resistor (R_REF), but not on the IDAC1 value. The absolute accuracy and temperature drift of the excitation current therefore does not matter. However, because the value of the reference resistor directly affects the measurement result, selecting a reference resistor with good initial accuracy and very low temperature coefficient is important to limit measurement errors introduced by R_REF.

The reference resistor R_REF not only serves to generate the reference voltage for the device, but also sets the voltages at the leads of the RTD to within the specified absolute input voltage range of the PGA. This is important in case PGA gains greater than 10 are used, because the PGA needs headroom from GND to operate when using gains greater than 10.

When designing the circuit, care must also be taken to meet the compliance voltage requirement of the IDAC. The IDAC requires that the maximum voltage drop developed across the current path to GND be equal to or less than the specified compliance voltage to operate accurately.

As stated in the Design Requirements, this design example describes the circuit implementation for a Pt100 element measuring temperatures ranging from –200°C to +850°C. The excitation current for the Pt100 is selected as I_IDAC1 = 400µA to meet the required power budget of this example. As mentioned previously, besides creating the reference voltage for the ADC, the voltage across R_REF also sets the absolute input voltages for the RTD measurement. In general, select the largest reference voltage possible that maintains the compliance voltage of the IDAC and meets the absolute input voltage requirement of the PGA. Setting the common-mode voltage at or below half the analog supply is a good starting point for a design. 1.6V is used as the target common-mode voltage in this example. Consequently, use Equation 25 to calculate the value for R_REF. The stability of R_REF is critical to achieve good measurement accuracy over temperature and time.

As a last step, select the PGA gain to match the maximum input signal to the FSR of the ADC. The resistance of a Pt100 increases with temperature. Therefore, the maximum voltage to be measured (V_INMAX) occurs at the positive temperature extreme. At 850°C, a Pt100 has an equivalent resistance of approximately 391Ω as per the NIST tables. The voltage across the Pt100 equates to Equation 26:

The maximum gain that can be applied when using a 1.6V reference is then calculated as (1.6V / 156.4mV) = 10.23. The next smaller PGA gain setting available in the ADS1x4S1x is 10. At a gain of 10, the device offers an FSR value as described in Equation 27:

This range allows for margin with respect to initial accuracy and drift of the IDAC and reference resistor.

To keep the ADC power consumption at a minimum, speed mode 0 (f_MOD = 32kHz) is selected using the SPEED_MODE[1:0] bits. And to meet the line-cycle rejection requirement at 50Hz and 60Hz, the 20SPS output data rate is selected using the STEPx_FLTR_OSR[4:0] bits. The measurement resolution (determined by the ADC noise) increases at the expense of higher power consumption, when selecting a faster speed mode with the same 20SPS output data rate setting. However the measurement accuracy (determined by the ADC DC errors, such as gain and offset error) is largely unaffected by the speed mode setting.

The primary purpose of the series resistors at the analog and positive reference inputs is to protect the device inputs from any overvoltage conditions. In case overvoltage conditions at the RTD terminals can occur in the application, select the series resistor value such that the currents into the analog and positive reference inputs get limited to less than 10mA. Series resistor values of 2.2kΩ are selected in this example to limit the input currents to less than 5mA when overvoltages up to ±10V are present at the RTD terminals. Consider the interaction of the series resistors with the input currents into the analog and reference inputs when selecting the resistor values. The voltage drop created across the series resistors causes a potential offset error. In addition, the series resistors together with the input capacitors form first order RC antialiasing filters. The exact corner frequency of the RC filters is not very critical with this delta-sigma ADC. A general recommendation is to select a corner frequency which is at least 10 times lower than the modulator frequency of the ADC.

After selecting the values for the IDAC, R_REF, PGA gain, and the series resistors, make sure to double check that the settings meet the absolute input voltage requirements of the PGA and the compliance voltage of the IDAC. Include the voltage drop created by IDAC1 across the RTD lead resistances and the series resistor at the IDAC1 output pin in the calculations.

Lead-wire compensation for 3-wire RTDs in this example is achieved by implementing a two-step measurement approach.

1. In step one, measure the voltage (V₁) between AIN3 and AIN4.
2. In a second measurement step, measure the voltage (V₂) between AIN3 and AIN6.

Equation 28 and Equation 29 represent the two measurements.

To assume that all three lead resistances have the same value, R_LEAD, is reasonable. Consequently, use Equation 30 to calculate the lead-wire compensated RTD voltage.

Table 9-2 shows the critical register bit settings for the various measurements in this design example.

For more information about RTD measurement circuits and the implementation using TI ADCs see the A Basic Guide to RTD Measurements application note. Various strategies for sensor fault detection using features similar to the ones integrated in ADS1x4S1x are discussed in the RTD Wire-Break Detection Using Precision Delta-Sigma ADCs application note. A software library using C code showing how to implement the RTD linearization algorithm in the host controller is available here.