SBASB61 August   2026 ADS114S18 , ADS124S18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Power-Scalable Speed Modes
      5. 7.3.5  Clock Source
      6. 7.3.6  Delta-Sigma Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Sinc3 and Sinc4 Filters
        2. 7.3.7.2 Sinc4 + Sinc1 Filter
        3. 7.3.7.3 FIR Filter
        4. 7.3.7.4 50Hz and 60Hz Line Cycle Rejection
        5. 7.3.7.5 Digital Filter Latency
        6. 7.3.7.6 Global-Chop Mode
      8. 7.3.8  Excitation Current Sources (IDACs)
      9. 7.3.9  Burn-Out Current Sources (BOCS)
      10. 7.3.10 Bias Voltage Generator (VBIAS)
      11. 7.3.11 General Purpose IOs (GPIOs)
        1. 7.3.11.1 ALERT Output
        2. 7.3.11.2 FAULT Output
      12. 7.3.12 Offset and Gain Calibration Coefficients
      13. 7.3.13 Digital Comparator
      14. 7.3.14 System Monitors
        1. 7.3.14.1 Internal Short (Offset Calibration)
        2. 7.3.14.2 Internal Temperature Sensor
        3. 7.3.14.3 External Reference Voltage Readback
        4. 7.3.14.4 Power-Supply Readback
      15. 7.3.15 Monitors and Status Flags
        1. 7.3.15.1 Reset (RESETn flag)
        2. 7.3.15.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.15.3 Reference Undervoltage Monitor (REF_UVn flag)
        4. 7.3.15.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.15.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.15.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.15.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.15.8 Digital Comparator Alert (COMP_ALERTn flag)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 RESET Pin
        3. 7.4.1.3 Reset by Register Write
        4. 7.4.1.4 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Sequencer Mode
          1. 7.4.2.3.1 Configuring the Sequencer
          2. 7.4.2.3.2 Starting and Stopping the Sequencer (START/STOP bits and START pin)
          3. 7.4.2.3.3 Sequencer Status Bits
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Register Map CRC
      11. 7.5.11 Conversion Data Format
  9. 8 Register Map
    1. 8.1 Status and General Configuration Page Registers
    2. 8.2 Step Configuration Page Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Interfacing With Multiple Devices
      4. 9.1.4 Device Initialization and Starting the Sequencer
      5. 9.1.5 Sequencer Configuration Strategy Example
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
      4. 9.2.4 Autonomous Power Supply Monitoring
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 1.74V to 3.6V, IOVDD = 1.65V to 5.25V, AVSS = DGND, internal reference, internal oscillator, all speed modes, all data rates, all gain settings, and global chop disabled (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Absolute input current(1) All gains, fDATA = 20SPS or 25SPS,
global chop enabled or disabled,
VAINx(MIN) ≤ VAINx ≤ VAINx(MAX), VIN = 0V		 –2 ±0.3 2 nA
Absolute input current drift(1) All gains, fDATA = 20SPS or 25SPS,
global chop enabled or disabled,
VAINx(MIN) ≤ VAINx ≤ VAINx(MAX), VIN = 0V		 2 pA/°C
Differential input current(1) All gains, fDATA = 20SPS or 25SPS,
global chop enabled or disabled,
VCM = (AVDD + AVSS)/2,
–VREF/Gain ≤ VIN ≤ VREF/Gain		 –1 ±0.1 1 nA
Differential input current drift(1) All gains, fDATA = 20SPS or 25SPS,
global chop enabled or disabled,
VCM = (AVDD + AVSS)/2,
–VREF/Gain ≤ VIN ≤ VREF/Gain		 2 pA/°C
PGA
Gain settings 0.5, 1, 2, 4, 5, 8, 10, 16, 20, 32, 50, 64, 100, 128, 200, 256
SYSTEM PERFORMANCE
Resolution (no missing codes) ADS114S1x 16 Bits
ADS124S1x 24
fDATA Output data rate Speed mode 0 (fMOD = 32kHz) 3.9 4k SPS
Speed mode 1 (fMOD = 256kHz) 10 32k
Speed mode 2 (fMOD = 512kHz) 10 64k
Speed mode 3 (fMOD = 1024kHz) 10 128k
INL Integral nonlinearity VCM = (AVDD + AVSS)/2, best fit 5 15 ppmFSR
VIO Input offset voltage TA = 25°C, gains ≤ 1, global chop disabled –350 ±50 350 µV
TA = 25°C, gains = 2 to 10, global chop disabled –200 ±20 200
TA = 25°C, gains ≥ 16, global chop disabled –50 ±10 50
TA = 25°C, gains ≤ 1, global chop enabled –6 ±0.5 6
TA = 25°C, gains ≥ 2, global chop enabled –2.5 ±0.2 2.5
Offset drift Gains ≤ 10, global chop disabled 50 300 nV/°C
Gains ≥ 16, global chop disabled 20 125
Gains ≤ 1, global chop enabled 10 50
Gains ≥ 2, global chop enabled 2 20
Gain error TA = 25°C, all gains, external reference –0.08 ±0.01 0.08 %
Gain drift All gains, external reference 0.5 2.5 ppm/°C
Noise (input-referred) See the Noise Performance section
CMRR Common-mode rejection ratio At dc 120 dB
fCM = 50Hz or 60Hz (±1Hz),
fDATA = 10SPS, 20SPS or 25SPS		 130
fCM = 50Hz (±1Hz), fDATA = 10SPS, 16.7SPS or 50SPS 130
fCM = 60Hz (±1Hz), fDATA = 10SPS or 60SPS 130
fCM = 50Hz or 60Hz (±1Hz), fDATA > 60SPS 120
PSRR Power-supply rejection ratio AVDD at dc 115 dB
IOVDD at dc 120
NMRR Normal-mode rejection ratio fIN = 50Hz or 60Hz (±1Hz), fDATA = 10SPS, sinc3 92 102 dB
fIN = 50Hz or 60Hz (±1Hz), fDATA = 10SPS, sinc3,
external fCLK = 4.096MHz		 102
fIN = 50Hz or 60Hz (±1Hz), fDATA = 10SPS, sinc4 122 136
fIN = 50Hz or 60Hz (±1Hz), fDATA = 10SPS, sinc4,
external fCLK = 4.096MHz		 136
fIN = 50Hz (±1Hz), fDATA = 16.7SPS, sinc3 91 102
fIN = 50Hz (±1Hz), fDATA = 16.7SPS, sinc3,
external fCLK = 4.096MHz		 102
fIN = 50Hz (±1Hz), fDATA = 16.7SPS, sinc4 121 135
fIN = 50Hz (±1Hz), fDATA = 16.7SPS, sinc4,
external fCLK = 4.096MHz		 135
fIN = 50Hz or 60Hz (±1Hz), fDATA = 20SPS 83 95
fIN = 50Hz or 60Hz (±1Hz), fDATA = 20SPS,
external fCLK = 4.096MHz		 95
fIN = 50Hz or 60Hz (±1Hz), fDATA = 25SPS 58 63
fIN = 50Hz or 60Hz (±1Hz), fDATA = 25SPS,
external fCLK = 4.096MHz		 63
fIN = 50Hz (±1Hz), fDATA = 50SPS, sinc3 91 101
fIN = 50Hz (±1Hz), fDATA = 50SPS, sinc3,
external fCLK = 4.096MHz		 101
fIN = 50Hz (±1Hz), fDATA = 50SPS, sinc4 121 135
fIN = 50Hz (±1Hz), fDATA = 50SPS, sinc4,
external fCLK = 4.096MHz		 135
fIN = 60Hz (±1Hz), fDATA = 60SPS, sinc3 91 103
fIN = 60Hz (±1Hz), fDATA = 60SPS, sinc3,
external fCLK = 4.096MHz		 103
fIN = 60Hz (±1Hz), fDATA = 60SPS, sinc4 122 137
fIN = 60Hz (±1Hz), fDATA = 60SPS, sinc4,
external fCLK = 4.096MHz		 137
VOLTAGE REFERENCE INPUTS
Absolute input current Reference buffer disabled, speed mode 0(2) –2 ±1 2 µA/V
Reference buffer disabled, speed mode 1(2) –7 ±6 7
Reference buffer disabled, speed mode 2(2) –8 ±7 8
Reference buffer disabled, speed mode 3(2) –9 ±8 9
Reference buffer enabled, speed mode 0 –2 ±0.2 2 nA
Reference buffer enabled, speed mode 1 4 9
Reference buffer enabled, speed mode 2 9 17
Reference buffer enabled, speed mode 3 17 33
INTERNAL VOLTAGE REFERENCE
VREF Output voltage (AVDD – AVSS) < 2.7V 1.25 V
(AVDD – AVSS) ≥ 2.7V 1.25, 2.5
Accuracy TA = 25°C –0.1 ±0.01 0.1 %
Temperature drift 14 35 ppm/°C
Output current VREF = 1.25V, sink or source –5 5 mA
VREF = 2.5V, (AVDD – AVSS) ≥ 2.75V, sink or source –10 5
IREF_SC Short-circuit current limit Sink or source ±30 mA
PSRR Power-supply rejection ratio AVDD at dc 90 dB
Load regulation Load current = –5mA to 0mA (source) 75 µV/mA
Capacitive load stability 50 100 1300 nF
Reference noise f = 0.1Hz to 10Hz, 100nF capacitor on REFOUT 4 ppmPP
Start-up time From power-down mode, 100nF capacitor on REFOUT, 0.01% settling 10 ms
INTERNAL OSCILLATOR
fOSC Frequency 4.096 MHz
Accuracy –1 1 %
TEMPERATURE SENSOR
TSOffset Output voltage TA = 25°C 120 mV
TSTC Temperature coefficient 400 µV/°C
VBIAS
Output voltage (AVDD + AVSS)/2 V
Capacitive load drive capability Sum of all capacitors connected to analog inputs where VBIAS is enabled. 10 µF
Output impedance 200 300 Ω
BURNOUT CURRENT SOURCES (BOCS)
Current settings 0.2, 1, 10 µA
Accuracy Sink and source ±2 %
EXCITATION CURRENT SOURCES (IDACS)
Current settings IDAC unit current = 1µA 1 to 100 µA
IDAC unit current = 10µA, (AVDD – AVSS) < 2.7V 10 to 500
IDAC unit current = 10µA, (AVDD – AVSS) ≥ 2.7V 10 to 1000
Compliance voltage IIDAC < 100µA, current changes by less than 1% from (AVDD – 1V) AVSS AVDD – 0.3 V
IIDAC ≥ 100µA, current changes by less than 1% from (AVDD – 1V) AVSS AVDD – 0.4
Accuracy TA = 25°C –3 ±0.4 3 %
Current mismatch between IDACs IIDAC ≤ 10µA, IDAC1 and IDAC2 set to same value,
TA = 25°C		 0.5 1.5 %
IIDAC ≥ 20µA, IDAC1 and IDAC2 set to same value,
TA = 25°C		 0.05 0.3
Temperature drift 25 150 ppm/°C
Temperature drift matching IIDAC ≤ 10µA, IDAC1 and IDAC2 set to same value 10 50 ppm/°C
IIDAC ≥ 20µA, IDAC1 and IDAC2 set to same value 1 10
MONITORS
THIOVDD_POR IOVDD POR release threshold 1.55 V
THAVDD_UV AVDD undervoltage threshold(3) 1.2 1.5 V
THREF_UV Reference undervoltage threshold(3) REF_UV_SEL = 0b 0.45 0.65 V
REF_UV_SEL = 1b 0.9 1.1
System monitor voltage readback accuracy (AVDD – AVSS) / 8 ±0.5 %
(IOVDD – DGND) / 8 ±0.5
VDLDO / 4 ±0.5
(VREFPx – VREFNx) / 8 ±0.5
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs)
VIL Logic input level, low AVSS AVSS + 0.3 (AVDD – AVSS) V
VIH Logic input level, high AVSS + 0.7 (AVDD – AVSS) AVDD V
VOL Logic output level, low IOL = 100µA, open-drain or push-pull output AVSS AVSS + 0.2 (AVDD – AVSS) V
VOH Logic output level, high IOH = –100µA, push-pull output AVSS + 0.8 (AVDD – AVSS) AVDD V
Input hysteresis 10 mV
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low DGND 0.3 IOVDD V
VIH Logic input level, high 0.7 IOVDD IOVDD V
VOL Logic output level, low IOL = 1mA DGND 0.2 IOVDD V
VOH Logic output level, high IOH = –1mA 0.8 IOVDD IOVDD V
Input hysteresis 180 mV
Input current DGND ≤ VDigital Input ≤ IOVDD –1 1 µA
ANALOG SUPPLY CURRENTS (AVDD = 3.3V, AVSS = DGND, External Reference, Reference Buffers Disabled, IDACs Disabled, VIN = 0V)
IAVDD Analog supply current Power-down mode 0.7 4 µA
Standby mode 15 25
Conversion mode, speed mode 0, gain = 0.5 to 2 60 68
Conversion mode, speed mode 0, gain = 4 and 5 61 71
Conversion mode, speed mode 0, gain = 8 to 50 68 78
Conversion mode, speed mode 0, gain = 64 to 256 63 73
Conversion mode, speed mode 1, gain = 0.5 to 2 155 175
Conversion mode, speed mode 1, gain = 4 and 5 180 200
Conversion mode, speed mode 1, gain = 8 to 50 225 255
Conversion mode, speed mode 1, gain = 64 to 256 280 310
Conversion mode, speed mode 2, gain = 0.5 to 2 345 380
Conversion mode, speed mode 2, gain = 4 and 5 390 430
Conversion mode, speed mode 2, gain = 8 to 50 485 540
Conversion mode, speed mode 2, gain = 64 to 256 705 790
Conversion mode, speed mode 3, gain = 0.5 to 2 600 655
Conversion mode, speed mode 3, gain = 4 and 5 705 780
Conversion mode, speed mode 3, gain = 8 to 50 935 1050
Conversion mode, speed mode 3, gain = 64 to 256 1155 1300
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3V, VREF = 2.5V)
IAVDD Analog supply current Internal voltage reference, speed mode 0 4.5 6 µA
Internal voltage reference, speed mode 1 25 28
Internal voltage reference, speed mode 2 35 40
Internal voltage reference, speed mode 3 65 75
Either REFP or REFN buffer enabled, speed mode 0
 4.5 6
Either REFP or REFN buffer enabled, speed mode 1 25 28
Either REFP or REFN buffer enabled, speed mode 2 35 40
Either REFP or REFN buffer enabled, speed mode 3 65 75
Both REFP and REFN buffers enabled, speed mode 0 6.5 9
Both REFP and REFN buffers enabled, speed mode 1 32 40
Both REFP and REFN buffers enabled, speed mode 2 50 60
Both REFP and REFN buffers enabled, speed mode 3 102 120
IDAC overhead, IDAC unit current = 1µA 4 6
IDAC overhead, IDAC unit current = 10µA 14 20
VBIAS (no load) 11 18
ANALOG SUPPLY CURRENTS (AVDD = 1.8V, AVSS = DGND, External Reference, Reference Buffers Disabled, IDACs Disabled, VIN = 0V)
IAVDD Analog supply current Power-down mode 0.5 4 µA
Standby mode 12 22
Conversion mode, speed mode 0, gain = 0.5 to 2 55 63
Conversion mode, speed mode 0, gain = 4 and 5 57 66
Conversion mode, speed mode 0, gain = 8 to 50 63 73
Conversion mode, speed mode 0, gain = 64 to 256 59 68
Conversion mode, speed mode 1, gain = 0.5 to 2 140 170
Conversion mode, speed mode 1, gain = 4 and 5 160 190
Conversion mode, speed mode 1, gain = 8 to 50 205 235
Conversion mode, speed mode 1, gain = 64 to 256 255 290
Conversion mode, speed mode 2, gain = 0.5 to 2 310 345
Conversion mode, speed mode 2, gain = 4 and 5 355 395
Conversion mode, speed mode 2, gain = 8 to 50 450 505
Conversion mode, speed mode 2, gain = 64 to 256 660 750
Conversion mode, speed mode 3, gain = 0.5 to 2 540 595
Conversion mode, speed mode 3, gain = 4 and 5 640 720
Conversion mode, speed mode 3, gain = 8 to 50 870 985
Conversion mode, speed mode 3, gain = 64 to 256 1080 1220
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 1.8V, VREF = 1.25V)
IAVDD Analog supply current Internal voltage reference, speed mode 0 3.5 5 µA
Internal voltage reference, speed mode 1 16 20
Internal voltage reference, speed mode 2 26 32
Internal voltage reference, speed mode 3 55 70
Either REFP or REFN buffer enabled, speed mode 0
 3.5 5
Either REFP or REFN buffer enabled, speed mode 1 16 20
Either REFP or REFN buffer enabled, speed mode 2 26 32
Either REFP or REFN buffer enabled, speed mode 3 55 70
Both REFP and REFN buffers enabled, speed mode 0 5.5 8
Both REFP and REFN buffers enabled, speed mode 1 25 30
Both REFP and REFN buffers enabled, speed mode 2 42 52
Both REFP and REFN buffers enabled, speed mode 3 100 120
IDAC overhead, IDAC unit current = 1µA 4 6
IDAC overhead, IDAC unit current = 10µA 14 20
VBIAS (no load) 11 18
DIGITAL SUPPLY CURRENTS (IOVDD = 3.3V, All Data Rates, SPI Not Active)
IIOVDD Digital supply current Power-down mode 2.2 20 µA
Standby mode, speed mode 0 8 26
Standby mode, speed mode 1 22 40
Standby mode, speed mode 2 32 50
Standby mode, speed mode 3 50 70
Conversion mode, speed mode 0 (OSR = 8) 11 30
Conversion mode, speed mode 1 (OSR = 8) 42 64
Conversion mode, speed mode 2 (OSR = 8) 72 100
Conversion mode, speed mode 3 (OSR = 8) 129 163
Conversion mode, speed mode 0 (OSR ≥ 64) 10 27
Conversion mode, speed mode 1 (OSR ≥ 64) 34 53
Conversion mode, speed mode 2 (OSR ≥ 64) 54 75
Conversion mode, speed mode 3 (OSR ≥ 64) 97 120
DIGITAL SUPPLY CURRENTS (IOVDD = 1.8V, All Data Rates, SPI Not Active)
IIOVDD Digital supply current Power-down mode 2 19 µA
Standby mode, speed mode 0 8 25
Standby mode, speed mode 1 22 40
Standby mode, speed mode 2 30 50
Standby mode, speed mode 3 48 66
Conversion mode, speed mode 0 (OSR = 8) 11 28
Conversion mode, speed mode 1 (OSR = 8) 41 63
Conversion mode, speed mode 2 (OSR = 8) 70 95
Conversion mode, speed mode 3 (OSR = 8) 127 160
Conversion mode, speed mode 0 (OSR ≥ 64) 9 27
Conversion mode, speed mode 1 (OSR ≥ 64) 33 52
Conversion mode, speed mode 2 (OSR ≥ 64) 53 74
Conversion mode, speed mode 3 (OSR ≥ 64) 94 120
(1) Input currents scale with speed mode, data rate, gain, and global-chop mode settings.
(2) Current is flowing into REFPx and out of REFNx.
(3) Undervoltage monitor always trips below the specified MIN value and never trips above the specified MAX value.