SBAU394B April   2022  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Quick Start Guide
  6. 2Hardware
    1. 2.1 ADC Analog Input Signal Path
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Power Supplies
    4. 2.4 ADC Input Clock (CLK) Options
    5. 2.5 Digital-to-Analog Converter (DAC)
    6. 2.6 Digital Interface
    7. 2.7 Connection to the PHI
    8. 2.8 Digital Header
  7. 3Software Installation
  8. 4EVM Configuration and GUI Operation
    1. 4.1 EVM Configuration
    2. 4.2 GUI Operation
      1. 4.2.1 EVM GUI Global Settings for ADC Control
      2. 4.2.2 Register Map Configuration Tool
      3. 4.2.3 Time Domain Display Tool
      4. 4.2.4 Spectral Analysis Tool
      5. 4.2.5 Histogram Tool
      6. 4.2.6 DAC Configuration Tool
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout
    3. 5.3 Bill of Materials
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7References
  12. 8Revision History

2.1 ADC Analog Input Signal Path

Connect analog inputs to the EVM using the terminal blocks associated with each ADC channel. The screw terminal blocks (J12, and J13) can interface directly with the leads of an external sensor input. Figure 2-1 depicts the input path for each ADC channel on the EVM while Table 2-1 lists the supported input options.

ADS1285EVM-PDK Input Terminal Blocks and Headers (Schematic)Figure 2-1 Input Terminal Blocks and Headers (Schematic)
Table 2-1 Analog Input Terminal Blocks (J12, J13)
Terminal BlockPinFunctionADS1285 Input Pin(s)
J121Channel 1 positive input+VINP1 (Eventually leading to AIN1P)
2GNDAGND and DGND
3Channel 1 negative input–VINN1 (Eventually leading to AIN1N)
J131Channel 2 positive input+VINP2 (Eventually leading to AIN2P)
2GNDAGND and DGND
3Channel 2 negative input–VINN2 (Eventually leading to AIN2N)

Do not apply an input such that the voltage on the input pins of the ADS1285 exceeds the absolute maximum ratings. For more details, see the ADS1285 data sheet.

R45 and R46 provide common-mode voltage paths for the channel 1 inputs. See Section 2.3 for more information. In addition, R43 and C29 (in combination with R47 and C31) provide the common-mode, low-pass filters for the positive and negative inputs, respectively. Furthermore, R44 and R40 in combination with C30 provides the differential low-pass filter used in antialiasing. The series impedance is kept relatively low to maintain adequate total harmonic distortion (THD) performance. Similar differential and common-mode, low-pass filter footprints are present on all inputs.

Specifically for channel 2, the default configuration is set up to use the DAC1282 on the input. As a result, the common-mode filters for this configuration are not populated, and R50, R54, and C33 are optimized for the output of the DAC. There are two options for connecting the DAC to the channel 2 of the ADS1285: using the direct output of the DAC1282 or the integrated switches of the DAC1282. By default, the direct output of the DAC1282 is used by populating R55 and R59. As a result, using the integrated switches is achieved by depopulating R55 and R59, populating R56 and R58, and configuring the DAC using the GUI as described in Section 2.5. For best THD performance (approximately a 1-dB difference), use the direct output. For maximum flexibility, use the integrated switches.

If necessary, use the Vocm circuit to bias a floating input (2-wire) sensor to the proper ADC input common mode level. Vocm is 2.5V with respect to GND using a unipolar power supply (AVDD1=5V, AVSS=0V with respect to GND). Vocm is 0V with respect to GND using a bipolar power supply (AVDD1=2.5V, AVSS=-2.5V with respect to GND). The Vocm voltage and buffer circuitry are installed by default on the EVM. The Vocm output header is not installed by default on the EVM. Refer to Figure 5-3 for the circuit schematic.