SBAU394B April   2022  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Quick Start Guide
  6. 2Hardware
    1. 2.1 ADC Analog Input Signal Path
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Power Supplies
    4. 2.4 ADC Input Clock (CLK) Options
    5. 2.5 Digital-to-Analog Converter (DAC)
    6. 2.6 Digital Interface
    7. 2.7 Connection to the PHI
    8. 2.8 Digital Header
  7. 3Software Installation
  8. 4EVM Configuration and GUI Operation
    1. 4.1 EVM Configuration
    2. 4.2 GUI Operation
      1. 4.2.1 EVM GUI Global Settings for ADC Control
      2. 4.2.2 Register Map Configuration Tool
      3. 4.2.3 Time Domain Display Tool
      4. 4.2.4 Spectral Analysis Tool
      5. 4.2.5 Histogram Tool
      6. 4.2.6 DAC Configuration Tool
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout
    3. 5.3 Bill of Materials
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7References
  12. 8Revision History

1.3 Specification

The following specifications are applicable to the ADS1285EVM board and the PHI board.

Table 1-2 ADS1285EVM-PDK Specifications
PARAMETERCONDITIONSVALUE
TemperatureRecommended operating free-air temperature range, TA15°C ≤ TA ≤ 35°C
Power supply input current range (unipolar or bipolar)Supply current range |Is|0.25A ≤ |Is| ≤ 0.5A
Power supply input voltage range (bipolar)Recommended voltage input range for J3 (-IN) versus AGND-6.5V ≤ -Vin ≤ -5.5V
Input voltage rangeAbsolute input voltage versus AGND for VINPx and VINNx

Buffer only

AVSS + 0.1V ≤ VINx ≤ AVDD1 - 0.1V

PGA enabled

AVSS + 1.1V ≤ VINx ≤ AVDD1 - 0.85V
EXT clockRecommended voltage range (VCLK) versus DGND, external source applied to J5Logic Level High (VCLKh)0.8×IOVDD ≤ VCLKh
Logic Level Low (VCLKl)VCLKl ≤ 0.2×IOVDD
Recommended frequency range (fCLK), external source applied to J53MHz ≤ fCLK ≤ 8.3MHz
External digital IOExternal logic levels connected to header J9 versus DGNDLogic Level High (VIOh)0.8×IOVDD ≤ VIOh
Logic Level Low (VIOl)VIOl ≤ 0.2×IOVDD
ADS1285 AVDD1 to AVSSRecommended voltage range, external source applied to J15-23V ≤ AVDD1 ≤ 5.25V
ADS1285 AVDD1 to AGNDRecommended voltage range, external source applied to J15-22.375V ≤ AVDD1
ADS1285 AVSS to AGNDRecommended voltage range, external source applied to J3-1-2.625V ≤ AVSS ≤ 0V
ADS1285 AVDD2 to AGNDRecommended voltage range, external source applied to J15-42.375V ≤ AVDD2 ≤ 5.25V
ADS1285 AVDD2 to AVSSRecommended voltage range, external source applied to J15-4AVDD2 ≤ 5.25V
ADS1285 IOVDD to DGND Recommended voltage range, external source applied to J15-6IOVDD not connected to CAPD pin2.7V ≤ IOVDD ≤ 3.6V
IOVDD connected to CAPD pin1.65V ≤ IOVDD ≤ 1.95V

ADS1285 VREFN to AVSS

Recommended voltage range (R42 removed), external source applied to J10-2AVSS-0.05V ≤ REFN
ADS1285 VREFP to AVSSRecommended voltage range (R38 removed), external source applied to J10-1REFP ≤ AVDD1+0.1V

ADS1285 VREF

Recommended voltage range (R38 and R42 removed), external differential source applied to J10

Reference voltage = 5V

4.9V ≤ VREF ≤ AVDD1-AVSS+0.1V
Reference voltage = 4.096V4V ≤ VREF ≤ 4.2V
Reference voltage = 2.5V2.4V ≤ VREF ≤ 2.6V