SBAU394B April   2022  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Quick Start Guide
  6. 2Hardware
    1. 2.1 ADC Analog Input Signal Path
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Power Supplies
    4. 2.4 ADC Input Clock (CLK) Options
    5. 2.5 Digital-to-Analog Converter (DAC)
    6. 2.6 Digital Interface
    7. 2.7 Connection to the PHI
    8. 2.8 Digital Header
  7. 3Software Installation
  8. 4EVM Configuration and GUI Operation
    1. 4.1 EVM Configuration
    2. 4.2 GUI Operation
      1. 4.2.1 EVM GUI Global Settings for ADC Control
      2. 4.2.2 Register Map Configuration Tool
      3. 4.2.3 Time Domain Display Tool
      4. 4.2.4 Spectral Analysis Tool
      5. 4.2.5 Histogram Tool
      6. 4.2.6 DAC Configuration Tool
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout
    3. 5.3 Bill of Materials
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7References
  12. 8Revision History

4.1 EVM Configuration

After unpacking, the EVM is already configured with the default jumper settings. Figure 4-1 shows the locations for the default jumpers and Table 4-1 shows the functions of the default shunts.

ADS1285EVM-PDK ADS1285EVM-PDK Jumper Default SettingsFigure 4-1 ADS1285EVM-PDK Jumper Default Settings
Table 4-1 Default Shunt Settings
Header DesignatorPositionFunction
J11[1-2]Enables the REF62x supply to VREFP
J4[1-2]Connects AVSS to GND for unipolar ADC supply mode
J7[3-4]Connects CLK to an 8.192-MHz source from the crystal oscillator
J10Not installedHeader to supply the external reference voltage to VREFN and VREFP
J1[1-2]DAC PWR: Connects the output of the U4 LDO (AVSS+5V) to the DAC analog supply pin (AVDD)
J1[3-4]DAC PWR: Connects the PHI digital supply (DVDD) to the DAC digital supply pin (DVDD)
J15[1-2]ADC PWR: Connects the output of the U2 LDO (AVDD1) to the ADC analog supply 1 (AVDD1)
J15[3-4]ADC PWR: Connects the output of the U3 LDO (AVDD2) to the ADC analog supply 2 (AVDD2)
J15[5-6]ADC PWR: Connects the PHI digital supply (DVDD) to the ADC digital supply (IOVDD)
J3Not installedHeader to supply the external input to U5 for the –2.5-V supply
J8Not InstalledDisables 8.192-MHz crystal oscillator

Table 4-2 lists the nominal voltages that result from the default configuration.

Table 4-2 Nominal Voltages Resulting From a Default Configuration
Supply NameVoltage (Referenced to GND)
AVSSGND (0V)
AVSS+5V5V
DVDD (IOVDD)3.3V
AVDD15V
AVDD23V
5.5V5.5V
REFP4.096V
–2.5VNA, external supply needed to generate –2.5V