SBAU394B April   2022  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Quick Start Guide
  6. 2Hardware
    1. 2.1 ADC Analog Input Signal Path
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Power Supplies
    4. 2.4 ADC Input Clock (CLK) Options
    5. 2.5 Digital-to-Analog Converter (DAC)
    6. 2.6 Digital Interface
    7. 2.7 Connection to the PHI
    8. 2.8 Digital Header
  7. 3Software Installation
  8. 4EVM Configuration and GUI Operation
    1. 4.1 EVM Configuration
    2. 4.2 GUI Operation
      1. 4.2.1 EVM GUI Global Settings for ADC Control
      2. 4.2.2 Register Map Configuration Tool
      3. 4.2.3 Time Domain Display Tool
      4. 4.2.4 Spectral Analysis Tool
      5. 4.2.5 Histogram Tool
      6. 4.2.6 DAC Configuration Tool
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout
    3. 5.3 Bill of Materials
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7References
  12. 8Revision History

2.4 ADC Input Clock (CLK) Options

The main ADC clock signal (CLK) generates the ADS1285 modulator clock (fMOD) in one of two ways:

  • A crystal oscillator and the accompanying clock dividers can provide a selectable frequency for the entire range of the ADC.
    • The onboard crystal oscillator (Y1) provides the nominal 8.192MHz clock frequency (default)
    • The dividers (U6) step down the frequency to 4.096MHz
    • J8 allows the user to select between these frequencies and connect them directly to CLK by using a shunt
  • Provide an external main clock to a subminiature version A (SMA) connector (J5) or to pins 4 or 2 of J7 when a shunt does not select the frequency from the crystal oscillator.
    • In this case, a shunt must not cover J7 so that CLK is connected to any of the crystal oscillator signals
    • Be sure to review the valid CLKIN input frequency in the data sheet
Note: All clock sources are sourced back to the PHI connector (J6) so that SCLK is synchronous to CLK.

Figure 2-6 shows a schematic for the clock source.

ADS1285EVM-PDK CLK Source (Schematic)Figure 2-6 CLK Source (Schematic)